Connected component labeling algorithm on binary interlaced video for use in FPGA

This article presents a modification of the known hardware-oriented algorithms for finding connected components in the binary video image, designed for interlaced scanning. The proposed variant of a scanning window for interlaced scanning and an algorithm of its pipeline processing in FPGA allow carrying out calculations in a streaming mode at the frame rate of 25 Hz without buffering. The existing algorithms require frame buffering as they are intended for progressive scanning.