Study of verification efficiency using PyUVM and SystemVerilog-UVM

Python, as a multi-paradigm language known for its ease of integration with other languages, has recently gained considerable attention among verification engineers. The Python-based verification environment uses open libraries such as PyUVM, which provides a Python-based implementation of UVM 1.2, and PyVSC, which promotes limited randomization and functional coverage. The purpose of this work is to evaluate the effectiveness of digital design verification using PyUVM and compare capabilities and performance indicators with the established SystemVerilog-UVM methodology.