Modeling fault tolerant element for aerospace computer complexes
Автор: Tyurin S.F.
Журнал: Сибирский аэрокосмический журнал @vestnik-sibsau
Рубрика: Авиационная и ракетно-космическая техника
Статья в выпуске: 1 т.18, 2017 года.
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For aerospace computer systems it is extremely urgent to develop radiation-resistant components. The methods of ensuring the radiation resistance by creating a special architecture - RHBD (Radiation Hardened by Design) include structural triple redundancy (Triple Modular Redundancy, TMR) or majority voting. Triple Module Redundancy Design Techniques with the majority element of the three-state buffers used when creating projects for the programmable logic Xilinx FPGAs Virtex type to reduce radiation-induced switching of logic elements and memory elements. In this electronic circuit parts used in the majority of schemes mentioned sources and documentation of manufacturers were not disclosed. In this regard, the analysis and modeling of such schemes in order to clarify their feature are of great interest. The buffer circuit requires wired “AND’’ using Pullup resistor. Running simulations of majority vote circuit based on the tri-state buffer output in system circuit simulation National Instruments Electronics Workbench Group. However, simulations show that the majority circuit given on the description is not workable. Nevertheless, in the in the datasheet states that in Virtex FPGA is used so-called Virtex Horizontal Bus Logic. Implemented majority function, converted on the basis of the distribution law of the Boolean algebra of logic. The paper proposes a scheme based on a two-stage connection buffers, which corresponds to the logic described in the datasheet. This scheme is consistent with one of the circuit in which two buffers are used at the output of each LUT. A variant of implementation, the appropriate description given in the manufacturer’s documentation, without disclosing detailed circuit design is offered. In the future, it is advisable to consider redundancy within their buffers.
Плис fpga, fpga, triple module redundancy, majority vote circuit, 3-state buffer
Короткий адрес: https://sciup.org/148177675
IDR: 148177675