Modeling of a fault tolerant element for aerospace computer complexes

The paper simulates CMOS radiation hardened by design logic element with transistor-level redundancy for high-reliability aerospace applications. This element was previously used as a functionally-complete tolerance (FPTE), however, when combined four inputs there is a possibility of failure of one parry of any transistor in the upper (connection “+” power bus) or the lower parts of the circuit (bus connection “zero volts”). Increasing the probability of failure-free operation is made possible by a logical repetition of the law. To implement 2AND-NOT it needs to increase the number of inputs up to eight elements. Quadruple transistor structures, parrying one failure in each quartet are proposed. In comparison with triple redundancy win can be provided by eliminating the majority body in some cases. In order to test the failover components in production and / or exploitation it is offered to use separate control power transistor wafers with testing after such power is supplied from a single source. Modeling is performed in the system NI Multisim 10 by National Instruments Electronics Workbench Group. Simulation confirms efficiency of the proposed technical solutions. We consider the static and dynamic modeling; the conclusion about the possibility of testing such elements by using separate power supply for redundant substrates transistors is made.