Method and system of error injection for testing the fault tolerance processor on-the board control system of spacecraft

Error injection method for testing onboard processors’ fault-tolerance is proposed. It is based on the modification of the on-chip debugging method which uses the test port of the processor. Unlike the basic method, error injection is made by a built-in hardware error injector rather than by an external computer. An error injection system architecture is developed for the proposed method. Using the processor test port injection module can read the data with the required address in the internal memory; inject errors by inverting the required bit; write back data with injected errors by the initial address. An implementation example of the proposed system is demonstrated. The procedure of injecting and correcting a single failure in the processor on-chip memory is described. It is shown that the proposed method does not introduce much excessiveness in the core architecture of the processor. As a result of experiments about 90 % of injected errors were detected and at least 92 % of them were corrected. Implementation of the hardware injector provides greater autonomy and realistic testing of the processor’s fault-tolerance.