2D Convolution Operation with Partial Buffering Implementation on FPGA

In the modern digital systems, the digital image processing and digital signal processing application form an integrated part in the system design. Many designers proposed and implemented various resources and speed efficient approaches in the recent past. The important aspect of designing any digital system is its memory efficiency. The image consists of various pixels and each pixel is again holds a value from 0 to 255 which requires 8 bits to represent the range. So a larger memory is required to process the image and with the increase in size of the image the number of pixels also increases. A buffering technique is used to read the pixel data from the image and process the data efficiently. In the work presented in this paper, different window sizes are compared on the basis of timing efficiency and area utilization. An optimum window size must be selected so as to reduce the resources and maximize the speed. Results show the comparison of various window operations on the basis of performance parameters. In future other window operation along with convolution filter like Adaptive Median filter must be implemented and used by changing the row and column values in Window size.