A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN
Автор: Dipak S. Marathe, Uday P. Khot
Журнал: International Journal of Image, Graphics and Signal Processing @ijigsp
Статья в выпуске: 11 vol.11, 2019 года.
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This paper proposes a 10-bit mixed current mode low power SAR ADC for sensor node application. The different entities of a successive approximation register (SAR) analog-to-digital converter (ADC) circuit has a hybrid or mixed mode approach i.e.,voltage mode regenerative comparator; mixed SAR logic; and current mode digital-to-analog converter (DAC). The performance limitation of speed and the kick-back noise of a dynamic comparator is resolved using duty cycle controlled regenerative comparator. A mixed mode logic of a SAR is partitioning the design into synchronous ring counter and asynchronous output register. The data shifting of a ring counter is with the common clock tick while the output register exchanged it asynchronously using handshake signals, resulting in a low power SAR. The current mode switching function in a DAC to reduce asynchronous switching effect resulting in a low energy conversion per step. In overall, the proposed mixed SAR ADC consumes a 41.6 power and achieves an SFDR 69.3 dB at 10 MS/sec and 1 V supply voltage. It is designed and simulated in the 0.18 m TSMC CMOS process.
Successive approximation register (SAR), mixed-mode, current-mode, regenerative -comparator, analog-to-digital-converter (ADC), digital-to-analog converter (DAC)
Короткий адрес: https://sciup.org/15017050
IDR: 15017050 | DOI: 10.5815/ijigsp.2019.11.06
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