A Centralized Controller as an Approach in Designing NoC

Автор: Abdolhossein Fathi, Keihaneh Kia

Журнал: International Journal of Modern Education and Computer Science (IJMECS) @ijmecs

Статья в выпуске: 1 vol.9, 2017 года.

Бесплатный доступ

This paper presents a new NoC architecture to improve flexibility and area consumption using a centralized controller. The idea behind this paper is improving SDN concept in NoC. The NoC routers are replaced with small switches and a centralized controller doing the routing algorithm and making control decisions. As one of the main desirable property of NoC is flexibility, in this work with the help of centralized controller, having different topologies and also having two separate networks in a single platform is possible. The other effects of this new scheme are power and area consumption which are investigated. Performance of the NoC is also studied with an analytical model and compared with the traditional NoC. The proposed NoC is implemented in VHDL, simulated and tested with ISE Xilinx.

Еще

Network on chip (NoC), software define network (SDN), centralized controller, flexibility, reconfigurability

Короткий адрес: https://sciup.org/15014939

IDR: 15014939

Список литературы A Centralized Controller as an Approach in Designing NoC

  • Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger, and Yatin Hoskote, "Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives", IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, vol. 28, no. 1, pp.3-21 , January 2009.
  • L. Benini and G. D. Micheli, "Networks on chips: a new Soc paradigm", IEEE transaction on Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
  • Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov and Resve A. Saleh, "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures", IEEE Trans. Computers, vol. 54, no. 8, pp. 1025-1040, 2005.
  • Shafi Jasuja, Parminder Singh,"Appraisement of IEEE 802.11s based Mesh Networks with Mean Backoff Algorithm," International Journal of Modern Education and Computer Science, vol.7, no. 10, pp.20-26, 2015.
  • Simon J. Hollis, Chris Jackson, Paul Bogdan and Radu Marculescu, "Exploiting Emergence in On-Chip Interconnects" IEEE Transactions On Computers, vol. 63, no. 3, pp. 570-582, March 2014.
  • Somulu Gugulothu and M. D. Chawhan, "Design and Implementation of various topologies for Networks on Chip and its performance evolution", International Conference on Electronic Systems, Signal Processing and Computing Technologies, Feb. 2014, DOI: 10.1109/ICESC.2014.10.
  • Liyaqat Nazir, Roohie Naaz Mir, "Realization of Efficient High Throughput Buffering Policies for Network on Chip Router", I. J. Computer Network and Information Security, vol. 7, pp. 61-70, 2016, "DOI: 10.5815/ijcnis.2016.07.08".
  • Mostefa Belarbi, "Formal and Informal Modeling of Fault Tolerant NoC Architectures", I.J. Intelligent Systems and Applications, vol. 12, pp. 32-42, 2015, "DOI: 10.5815/ijisa.2015.12.03".
  • Paul Goransson and Chuck Black, "Software Defined Networks, A Comprehensive Approach", Elsevier Inc., First Edition, 2014.
  • Diego Kreutz, Fernando M. V. Ramos, Paulo Verissimo, Christian Esteve Rothenberg, Siamak Azodolmolky and Steve Uhlig, "Software-Defined Networking: A Comprehensive Survey", in Proceedings of the IEEE 103(1), pp. 14-76, June 2014.
  • Débora Matos, Caroline Concatto, Márcio Kreutz, Fernanda Kastensmidt, Luigi Carro, and Altamiro Susin, "Reconfigurable Routers for Low Power and High Performance", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 11, pp. 2045-2057, Nov. 2011.
  • Brugge, Michael, "Design and Evaluation of a Parameterizable NoC Router for FPGAs", Electronic Theses and Dissertations. Paper 115, 2009.
  • Anuprita.S. Kale, 2 Prof. M.A.Gaikwad, "Design and Analysis of On-Chip Router for Network on Chip", International Journal of Emerging Technology and Advanced Engineering, Volume 2, Issue 1, pp. 182-186, Jan. 2012.
  • Wooyoung Jang and David Z. Pan, "An SDRAM-Aware Router for Networks-on-Chip", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 10, pp. 1572-1585, Oct. 2010.
  • Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin and Marcio Kreutz, "NoC Power Optimization Using a Reconfigurable Router", IEEE Computer Society Annual Symposium on VLSI, May 2009, DOI: 10.1109/ISVLSI.2009.7.
  • R.Parthasarathi,P.Karunakaran,S.Venkatraman,T.R.DineshKumar,I.HameemShanavas,"Design Of High Performance Reconfigurable Routers Using Fpga", IJIEEB, vol.4, no.4, pp.46-52, 2012.
  • Bjerregaard and S. Mahadevan, "A Survey of Research and Practices of Network-on-Chip", ACM Computer Surveys, vol. 38, no. 1, 2006, DOI:10.1145/1132952.1132953
  • Woojoon Lee, Shuang Zhao, Xiaofang Zhou and Gerald E. Sobelman, "Software Defined Radio Architecture Using a Multicasting Network-on-Chip", International Conference on Information, Communications and Signal Processing, Dec. 2009, DOI: 10.1109/ICICS.2009.5397565.
  • Liu Cong, Wang Wen and Wang Zhiying, "A Configurable, Programmable and Software-Defined Network on Chip", IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA), Sep. 2014, DOI: 10.1109/WARTIA.2014.6976396.
  • Junhui Wang, Ming Zhu, Chao Peng, Lewen Zhou, Yue Qian and Wenhua Dou, "Software-Defined Photonic Network-on-Chip", Third International Conference on e-Technologies and Networks for Development (ICeND), May 2014, DOI: 10.1109/ICeND.2014.6991365.
  • R. Sandoval-Arechiga, J. L. Vazquez-Avila, R. Parra-Michel, "Shifting the Network-on-Chip Paradigm Towards a Software Defined Network Architecture", International Conference on Computational Science and Computational Intelligence, Dec. 2015, DOI: 10.1109/CSCI.2015.45.
  • R. Sandoval-Arechiga, R. Parra-Michel, J. L. Vazquez-Avila, J. Flores-Troncoso and S. Ibarra-Delgado, "Software Defined Networks-on-Chip for Multi/Many-Core Systems: A Performance Evaluation", ANCS '16, pp. 129-130, March 17-18, 2016, Santa Clara, CA, USA.
  • Pradeep Kumar Keshwani, Ravi Sankar Shukla and Apurva Agarwal, "Performance Analysis of Mesh, Torus and Folded Torus under Broadcasting, using Distance Vector Algorithm", International Journal Of Engineering And Computer Science, vol. 3, no. 6, pp. 6593-6597, Jun. 2014.
  • Pedram Rajabzadeh, Hamid Sarbazi-Azad, Hamid-Reza Zarandi, Ebrahim Khodaie, Hashem Hashemi-Najafabadi, Mohamed OuldKhaoua, -Performance modelling of n-dimensional mesh networks, Journal of Performance Evaluation, Volume 67, Issue 12, pp. 1304-1323, December 2010.
  • Umit Y. Ogras, Paul Bogdan, and Radu Marculescu, "An Analytical Approach for Network-on-Chip Performance Analysis", IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 2001-2013, Dec. 2010.
Еще
Статья научная