A Low Power BIST TPG for High Fault Coverage
Автор: R.Varatharajan, Lekha R.
Журнал: International Journal of Information Engineering and Electronic Business(IJIEEB) @ijieeb
Статья в выпуске: 4 vol.4, 2012 года.
Бесплатный доступ
A low hardware overhead scan based BIST test pattern generator (TPG) that reduces switching activities in circuit under test (CUTs) and also achieve very high fault coverage with reasonable length of test sequence is proposed. When the proposed TPG used to generate test patterns for test-per-scan BIST, it decreases the number transitions that occur during scan shifting and hence reduces the switching activity in the CUT. The proposed TPG does not require modifying the function logic and does not degrade system performance. The proposed BIST comprised of three TPGs: Low transition random TPG (LT-RTPG), 3-weight weighted random BIST (3-weight ERBIST) and Dual-speed LFSR (DS-LFSR). Test patterns generated by the LT-RTPG detect the easy-to-detect faults and remain the undetected faults can be detected by the WRBIST. The 3-weight WRBIST is used to reduce the test sequence lengths by improving detection probabilities of random pattern resistant faults (RPRF). The DS-LFSR consists of two LFSR's, slow LFSR and normal–speed LFSR. The DS-LFSR lowers the transition density at their circuit inputs.
Built-in self-test (BIST), switching activity, low power testing, test pattern generator
Короткий адрес: https://sciup.org/15013134
IDR: 15013134
Список литературы A Low Power BIST TPG for High Fault Coverage
- Seongmoon Wang, "A BIST TPG for Low Power Dissipation and High Fault Coverage", IEEE TRANSACTIONSON VLSI SYSTEMS, VOL.15,NO.7,JULY2007.
- Malav Shah and Dipankar Nag choudhuri, "BIST Scheme for Low Heat Dissipation and Reduced Test Application Time" 2006 IFIP.
- S.Wang and S.K.Gupta,LT-RTPG: A New Test-Per-Scan BIST TPG for Low Switching Activity, IEEE Trans.CAD.Integr. Circuits Syst., vol.25,no.8,pp.1565-1574,Aug.2006.
- Jiann-Chyi Rau, Ying-Fu Ho and Po-Han Wu, "A Novel Reseeding Mechanism for Pseudo Random testing of VLSI circuits", IEEE 2005.
- Chaowen Yu, Sudhakar M. Reddy and Irith Pomeran "Circuit Independent Weighted Pseudo-Random BIST Pattern Generator", 14th ATS symposium, IEEE2005.
- Chun-Yi Lee and Chien-Mo Li, " Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique", IEEE2005.
- Chaowen Yu, Sudhakar M. Reddy and Irith Pomeranz, "Weighted Pseudo-Random BIST for N-detection of Single Stuck-at Faults", 13th ATS symposium, IEEE2004.
- N.Z.Basturkmen,S.M.Reddy,and I.Pomeranz, A low power pseudo-random BIST technique, Proceedings of 8th IEEE International On-LineTesting Workshop (IOLTW'02), IEEE2002.
- Seongmoon Wang, Sandeep K. Gupta, "DS-LFSR: A New BIST TPG for Low Heat Dissip- ation", International Test Conference, IEEE1997.
- Seongmoon Wang, "Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST", ITC, IEEE1997.
- Parag K.Lala,"Digital Circuit Testing and Testability".
