A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network
Автор: Pouya Asadi
Журнал: International Journal of Information Engineering and Electronic Business(IJIEEB) @ijieeb
Статья в выпуске: 4 vol.7, 2015 года.
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In this paper, a new multiplier is presented which uses modified fourteen transistor adder and optimized hybrid counter for partial product reduction step. Conventional adder is modified to improve Wallace tree functionality. Reducing critical path in counter structure can reduce VLSI area in whole multiplier structure. This paper uses a new structure in partial product reduction step to increase speed. Four to two compressors are used in modified Wallace structure to minimize the critical path. In final addition step of algorithm a new carry lookahead network is presented which adds two final operands efficiently. It uses dynamic CMOS in transistor level to reduce power consumption. Proposed multiplier reduces critical path, increases speed and decreases wiring problems in compare with previous algorithms efficiently. A new Booth encoder is presented in radix 16 circuitry. It decreases number of partial products while hardware overhead is minimized.
Adder, Booth encoder, CMOS, Multiplier, VLSI
Короткий адрес: https://sciup.org/15013351
IDR: 15013351
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