Algorithm for choosing the optimal set of configurable self-timed logic gates

The article describes the developed algorithm for choosing the optimal set of new configurable strictly self-timed (SST) logic elements, which takes into account complex characteristics, such as: the number of transistors, area, time delay and power consumption. The following proposed universal logic elements are considered as options as part of a configurable logic block of programmable logic integrated circuits (FPGAs): SST function generator based on standard logic elements of the uncommitted logic array - ULA, SST function generator based on universal logic element of programmable logic integrated circuits - FPGA (LUT-ST), SST generator of function systems based on the decoding of the water set DC LUT-ST and SST equivalent of a programmable logic matrix - PLM (DNF-LUT-ST).