Analysis of the SRAM cell as SR flip-flop and Moore finite-state machine

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In the article is described the analysis of the SRAM cell as SR flip-flop and Moore finite-state machine. A six-transistor CMOS SRAM cell is modeling by NI Multisim (National Instruments Electronics Workbench Group).

Шеститранзисторная ячейка памяти sram, sram cell, sr триггер, moore finite-state machine, sr flip-flop, wired and, ni multisim

Короткий адрес: https://sciup.org/14729929

IDR: 14729929

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