Hardware implementаtion of systematic polar encoding

Encoding information with error correcting codes provides ability to control the integrity of transmitted messages. In some cases, it also allows correcting errors that appeared during transmission over noise channel. The article provides description of polar codes - binary block linear error correcting codes that achieve capacity for symmetric memoryless channels. Polar codes are based on the channel polarization operation based on idea of polarization transformation of N-bit binary symmetric memoryless channel. The article describes non-systematic and systematic polar encoding operations with bit reversed and non-reversed bit order. It also describes systematic polar encoding method based on two applications of non-systematic encoding of polar codes. The paper introduces polar codes precoding operation which means expansion of information vector of length K into vector of length N corresponding to some polar code C. There is a hardware implementation of precoding operation based on usage of shift registers, which allows precoding any vector of length K corresponding to any (N, K) polar code. The article gives a review and comparison of non-systematic polar encoder architectures with bit reversed and non-reversed bit order. Both architectures are based on pipelined computation principle, partially parallel and have input capacity P multiple of the codeword length N. The paper proposes pipelined architecture of systematic polar encoder for (32, 16) non-reversal polar codes including precoder block and two non-systematic encoders, pipeline diagram is provided. There are two methods of architecture scaling. Scaling in width means increase of capacity of input signal P, scaling in length means increase of number of pipeline stages for each non-systematic encoder. Proposed encoder is simulated using Altera Quartus II 13.0 and ModelSim 10.1. The results of simulation are fully coincide with results of modeling using MATLAB R2016b.