Area & power optimization of asynchronous processor using Xilinx ISE & Vivado
Автор: Archana rani, Naresh Grover
Журнал: International Journal of Information Engineering and Electronic Business @ijieeb
Статья в выпуске: 4 vol.10, 2018 года.
Бесплатный доступ
As the technology era has been changing, the designing pattern of an IC is also changing. An IC de-signing is now divided into two definite fields i.e. Front-End design and Back-End design. The Front-End design is using HDLs (Hardware Description Languages i.e. VHDL or Verilog) and the verification of those ICs, whereas the Back-End Design is related to the Physical Design techniques. But both of the IC design techniques required some extra efforts in terms of their Speed, Shape, and Size, which needs the Optimization efforts. This pa-per deals with the area and power optimization efforts in terms of the logic utilization by using XST & Vivado Tools. After applying area optimization techniques i.e. Logic Optimization, LUT mapping and Resource Sharing etc. on already designed asynchronous microprocessor to be used as model for proposed optimization, reasonable results in terms of power and area utilization have been achieved.
FPGA, Microprocessor design, Optimiza-tion, Xilinx Synthesis Tool (XST) and Vivado
Короткий адрес: https://sciup.org/15016138
IDR: 15016138 | DOI: 10.5815/ijieeb.2018.04.02
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