Area Reduction in Redundancy Module for an ECC Based Fault Tolerance in Digital Filters
Автор: Jyoti Saini, Harpal Singh
Журнал: International Journal of Image, Graphics and Signal Processing(IJIGSP) @ijigsp
Статья в выпуске: 8 vol.8, 2016 года.
Бесплатный доступ
Due to the wide usage of digital filters in communication systems, reliability and area has to be considered and deficiency tolerant channel usage are required. Throughout the decades, there are number of techniques that have been proposed to achieve fault tolerance. As the number of parallel filters are increasing in any digital device, the redundancy module should also be small in size. In this paper, a simple technique of constant multiplication reduction method is introduced in the Error Correction Codes (ECC) based parallel filters in order to reduce the size of the redundant module. Main agenda is to reduce the size of the redundant module by not affecting the functionalityof the system. The proposed scheme is coded in HDL and simulation results are obtained by using Xilinx 12.1i. The presented result shows that the slices can be reduced and hence the size. As a result of reduction in size, the optimization of area can also be concluded.
Fault tolerance, ECC, Xilinx, Slices, LUT, Digital filters
Короткий адрес: https://sciup.org/15014003
IDR: 15014003
Список литературы Area Reduction in Redundancy Module for an ECC Based Fault Tolerance in Digital Filters
- DevanandBhosleet al., "Medical Image Denoisings Using Bilateral Filter," I.J. Image, Graphics and Signal Processing, 2012, 6, 36-43, published online July 2012 in MECS.
- Z. Gao et al., "Fault tolerant parallel filters based on error correction codes," IEEE Trans. Very Large Scale Integr. Syst., vol. 23, no. 2, pp. 384–387, Feb. 2015.
- Z.Gao et al., "Efficient coding schemes for fault- tolerant parallel filters,"IEEE trans .on circuits and systems. vol.62.no.7,July 2015
- M. Nicolaidis, "Design for soft error mitigation," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 405–418, Sep. 2005.
- T. Hitana and A. K. Deb, "Bridging concurrent and non-concurrent error detection in FIR filters," in Proc. Norchip Conf., 2004, pp. 75–78.
- B. Shim and N. Shanbhag, "Energy-efficient soft error-tolerant digital signal processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336–348, Apr. 2006.
- P. Reviriego, C. J. Bleakley, and J. A. Maestro, "Strutural DMR:A technique for implementation of soft-error-tolerant FIR filters,"IEEE Trans. Circuits Syst., Exp. Briefs, vol. 58, no. 8, pp The paper presents the implementation of a. 512 516,Aug. 2011.
- Y.-H. Huang, "High-efficiency soft-error-tolerant digital signal processing using fine-grain subword-detection processing," IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 18, no. 2pp.291–304, Feb. 2010.
- Z. Gao, W. Yang, X. Chen, M. Zhao, and J. Wang, "Fault missing rate analysis of the arithmetic residue codes based fault-tolerant FIR filter design," in Proc. IEEE IOLTS, Jun. 2012, pp. 130–133.
- A. Sibille, C. Oestges, and A. Zanella, MIMO: From Theory to Implementation. San Francisco, CA, USA: Academic Press, 2010.
- P. P. Vaidyanathan. Multirate Systems and Filter Banks. Upper Saddle River, NJ, USA: Prentice-Hall, 1993.
- P. Reviriego, S. Pontarelli, C. Bleakley, and J. A. Maestro,"Area efficient concurrent error detection and correction for parallel filters," IET Electron. Lett., vol. 48, no. 20, pp. 1258–1260, Sep. 2012.
- S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall. 2004.
- IzzatAlsmadiet al., "Test cases reduction and selection optimization in testing web services," I.J. Information Engineering and Electronic Business, 2012, 5, 1-8 Published Online October 2012 in MECS.
- Sanjay singhet al., "Real- time FPGA based implementation of colour image edge detection,"I.J. Image, Graphics and Signal Processing, 2012, 12, 19-25 Published Online November 2012 in MECS.
