Design and analysis of tunnel FET for low power high performance applications

Published Online January 2018 in MECS DOI: 10.5815/ijmecs.2018.01.07

Tunnel FET device is one of the promising novel devices which is giving a threat to the conventional MOSFET device to be used for low power applications. TFET device operation is based upon band to band tunneling (BTBT) mechanism and it possesses very low leakage current and steep subthreshold slope. Subthreshold swing in case of MOSFET is ln(10) (KT/q) and at room temperature (300K), SS value is around 60

mV/dec. This fundamental challenge of reducing the SS value below 60mV/decade at room temperature can be easily overcome using a TFET device. TFET device also possess better Ion/Ioff ratio as compared to MOSFET and it is because of its low off current that TFET device is gaining confidence to be used in designing SRAMs for ultra low power applications. It is a well known fact that cache memory occupies almost 50% of the on chip area of the processor and reducing leakage in cache memory is a serious concern that needs to be addressed. A tunnel FET device possessing low off state current seems to be an immediate remedy for reducing leakage in cache memory.

A detailed description of zener tunneling and avalanche breakdown mechanism in As implanted n-p junctions had been described in detail in [1]. The main issue with a single gate TFET device is very low value of on current and poor subthreshold swing. A novel design for the double gate TFET (DGTFET) was proposed for the first time using high K dielectric material [2]. This novel device achieved SS of 57 mV/dec and an exceptionally high Ion/Ioff ratio. A novel structure of TFET device exhibiting higher on current than a conventional p-i-n TFET device was proposed in [3]. This structure was named as pocket doped TFET and has a pocket on the source side to improve the on current. Ambipolarity reduction was achieved using low doped drain extension. Modification in the TFET structure was required to be done so as to address the issue of poor on current and to achieve SS value of less than 60mV/dec. Different structures were proposed in the literature to overcome these limitations. To improve the tunneling current, low bandgap materials (eg. SiGe, Ge, InGaAs, InAs) have been widely explored for TFET prototype device design [4]. Electron Hole bilayer Tunnel FET (EHBTFET) structure had been proposed in [5] and this structure exploits the asymmetric bias configuration of a DGTFET device thereby creating the two carrier layers instead of one inside the thin silicon film. The bias applied at the bottom gate is fixed and the top gate bias is used to change the electron layer concentration thereby controlling the drain current. A novel device structure called Sandwitch Tunnel Barrier FET (STBFET) had been proposed in [6]. This novel structure overcomes the issue of large voltage overshoot that occurs in conventional TFET device. Schottky Tunneling Source SOI MOSFET (STS-FET) proposed in [7] has gate controlled schottky barrier tunneling at the source and possesses high immunity to short channel effects. Analysis of the leakage current of the pocket doped TFET device shows very less change with change in temperature [8]. This signifies that pocket doped TFET device has better temperature immunity as compared to MOSFET and conventional TFET device. Vertical InGaAs/InP heterojunction TFET had been proposed in [9] for the first time. Gate overlapped source and pocket doping approach were used in [10] to improve the performance of InGaAs/InP HTFET device. The concept of leakage reduction in vertical TFET structure was proposed in [11]. This new InAs based vertical TFET device structure achieves better Ion close to ITRS requirement and SS value of less than 60 mV/dec. The discussions made till now signifies that TFETs hold promising future in the IC world and are being explored by research fraternity over the years [12,29].

The rest of the paper is organized as follows: Section II describes the TFET device structure and its operation in detail. Concept of Subthreshold swing and challenges related to TFET device are discussed in section III. Section III also highlights the models used for performing simulations on Visual TCAD tool. Related work that is reported in the literature is presented in section IV. Simulation results of different TFET devices simulated in TCAD tool are highlighted in Section V. The effect of mole fraction parameter (x) on the performance of III-V HTFET device is discussed in Section VI and finally in Section VII conclusions are drawn.

• II.    Tfet Device Structure and Its Operation

The basic structure of nTFET consists of a p-i-n diode with the gate region covering the entire intrinsic region. Fig.1 shows the structure of nTFET in double gate configuration with p+ source region and n+ drain region. The structure can be regarded as a gated p-i-n diode in which tunneling of electrons takes place between p+ source and intrinsic region.

In the off state the energy barrier height is high enough so that the electrons cannot tunnel through the thick depletion region which exists across p+ source and intrinsic region and hence the off current is very low. When positive voltage is applied to the n+ region and gate is also made positive with reference to the p+ source region then there occurs band bending and reduction in the energy barrier height which increases the probability of inter-band tunneling of electrons from valance band of p+ source region to the conduction band of the intrinsic region. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling [13].

Fig.1. Basic DGTFET device structure.

Energy band diagram at different V GS values shows band gap narrowing effect and band bending which increases the tunneling probability across the tunnel junction. Fig.2. shows the band diagram plot of n-type DGTFET device at V GS =0V and V DS =1V and Fig.3 shows the band diagram plot at V_GS=1V and V_DS=1V.

Fig.2. Band diagram of DGTFET device at V GS =0V and V DS =1V.

Fig.3. Band diagram of DGTFET device at V GS =1V and V DS =1V

Comparative band diagram is shown in Fig.4. It clearly shows that band gap reduction takes place with change in V GS value. A point to note is that both band bending and band gap narrowing takes place with increase in V GS value.

The challenge of enhancement of the on current in tunnel FET can be addressed by using a lower energy band gap material rather than silicon thereby enhancing the tunneling probability across the tunnel junction. Materials like Ge, InAs, III-V compound semiconductors exhibits lower Eg value and can be used for the fabrication of TFET device. On current of the similar order can be achieved as it can be achieved using a MOSFET device. Using germanium in the source region can lead to small tunnel band gap and leads to improvement in the energy efficiency of the TFET device [14].

Boucart et al. [12] had proposed an analytical expression that can be used for the calculation of average sub-threshold swing of TFET device.

Average Subthreshold Swing =

Vth - Voff

1   ( Ith log

I M

Fig.4. Comparative Band diagram of DGTFET device.

where Voff is the gate source voltage at which drain current is minimum ( Ioff ), Vth is the threshold voltage at the threshold point (point at which Ids is 10^-7 A/um). A practical expression for calculating the effective sub threshold swing of TFET device was proposed in [16]. According to this new practical definition:

Vth = ^Vdd and Ith = Ids(Vgs=Vdd/2) 2

Voff = 0 and Ioff = Ids (Vgs=0)

Hence Subthreshold Swing expression can be rewritten as-

SS = Vdd! [2 log( Ith / loff )].

• III.    Subthreshold Swing and Reliability Issues

Subthreshold swing in TFETs is defined in the same way as it is done in MOSFETs which means that it is the gate voltage which must be applied with respect to source so as to increase the drain current by one decade. A formula for calculating the subthreshold swing of TFET is proposed in [15]. This formula shows that SS of TFET is not limited to 60mV/decade. Mathematically Subthreshold Swing (SS) can be expressed as-

Subthreshold Swing =

dVg d (log Id )

mV / dec .

The subthreshold swing of MOSFET is limited to 60mV/dec at T=300K (room temperature) and this limitation can be overcome in TFETs which rely on interband tunneling via barrier width modulation rather than the formation of weak inversion channel between source and drain. Point sub threshold swing is the smallest value of the subthreshold swing on the ID-VG curve and on the other hand average subthreshold swing is calculated from the point where the device starts to turn on up to the threshold point (defined using constant current method [12]). The subthreshold swing in TFET is strongly dependent on the gate bias and for analyzing the switching performance it is better to consider average subthreshold swing rather than the point subthreshold swing. Literature indicates that the inherent issue of lower tunneling current that exists in silicon because of relatively higher energy band gap and lower effective tunneling mass has encouraged the designers to deploy lower band gap materials for the fabrication of TFET. Materials like Ge, InAs, GNRs, Heterojunction materials (SiGe/Si, AlGaSb/InAs, AlGaAsSb/InGaAs) etc. leads to a significant increase in the on current of TFET.

SS value decreases as Vgs value decreases. Vgs directly controls the tunnel junction bias (band overlap). Gate is placed to align the field with the internal field at the tunnel junction. Gate field adds to the internal field and increases the tunneling probability.

Cogenda Visual TCAD is used for performing device simulations. Kane’s Local BTBT model is used along with SRH model for device simulation. For mobility Lombardi model is used in this work. A method to calculate the parameters A and B of Kane’s direct and indirect tunneling models at different tunneling directions for Si, Ge and Si 1-x Ge x was discussed in [17]. The calculation of band-to-band generation rate in uniform electric field reveals that direct tunneling always dominates over indirect tunneling in Ge [17].

Kane’s Band to Band Tunneling Model:

Kane’s tunneling model is used in the simulator to calculate the carrier generation by band to band tunneling phenomenon. The carrier generation rate is calculated using the following expression derived from [17].

²         (               F ^3/2

Challenges in TFET:

Unlike CMOS, TFETs exhibit unidirectional conduction due to their asymmetric source-drain architecture [18,31]. TFET operates at low supply voltage range (V_dd< 0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from practical application perspective [19]. Subthreshold swing of TFET is found to be more robust against PBTI as compared with MOSFETs [20]. Charges present in the Si-Oxide interface and Oxide-Oxide interface affects the performance of the TFET device. Tunnel FETs also show relatively less variation to fixed interface charges and can replace MOSFETs in circuits to combat against NBTI and PBTI effects [21]. Investigation of p-n-i-n TFET device carried out in [22] reveals that TFET structure has improved reliability as compared to conventional TFET structure. Reduced interface trap generation and gate leakage is seen in p-n-i-n TFET along with less variation in the threshold voltage with change in the oxide thickness and Si film thickness. The gate dielectric plays an important role in enhancing the performance of a p-n-p-n TFET device. In p-n-p-n TFET device use of high gate dielectric constant is preferable for enhancing the gate control over the channel, while a low fringe dielectric constant is useful to increase band to band tunneling probability [23]. Use of spacer in TFET device leads to suppression in the ambipolar conduction [24]. Overlapping the gate on the drain can also suppress the ambipolar conduction, which is an inherent property of a TFET device [25]. Doping Less Tunnel FET device is expected to be free from random dopant fluctuation [26] and this configuration also possesses similar performance as that of the corresponding doped TFET device. Use of TFET device in low power high performance application circuits like SRAM can lead to several advantages like improvement in the noise margins, power reduction and reliability. Different SRAM cell topologies are proposed in [12,19,27] have shown tremendous performance under ultra low supply voltage and thereby showing the possibility of designing complete TFET based SRAM. DGTFET-based dynamic memory at sub-100-nm regime has been discussed in detail in [30] with main emphasis on device optimization by tuning the misalignment, lateral spacing between the gates ( L gap ) and an underlap ( L un ) between the back gate and drain region.

• IV.    Related Work