Design and Implementation of a Power Efficient Pulse-shaping Finite Impulse Response Filter on a Field Programmable Gate Array Chip

This paper presents one novel algorithm for minimization of non-zero coefficients of Finite Impulse response (FIR) pulse-shaping filter, mostly employed in practical digital communication system to alleviate the difficulties resulting from Inter Symbol Interference (ISI), followed by its hardware optimization on a Field Programmable Gate Array (FPGA) chip . Filter performance has been demonstrated through the inclusion of impulse response, magnitude spectrum and requirement of various hardware blocks. The supremacy of our algorithm has been substantiated by comparing its performance with other existing models of different length. From the simulation results, it has been concluded that the proposed FIR filter provides a considerable reduction in the number of non-zero coefficients without affecting its performance significantly.