Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

Автор: Mohammad Reza Reshadinezhad, Niloofar Charmchi, Keivan Navi

Журнал: International Journal of Modern Education and Computer Science (IJMECS) @ijmecs

Статья в выпуске: 9 vol.7, 2015 года.

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Multiplication scheme is one of the most essential factors, which is time consuming. Designers and manufacturers of processors emphasis on methods which would not only perform the multiplication scheme in a rapid manner, but would reduce the physical aspect of the design as well; hence, a reduction in power consumption. Addition is one of the fundamental factors in multiplication. Pre-designing of circuits and transistors' levels used to be made through Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but now, due to scaling and difficulties thereof, new technologies like Single Electron Transistor (SET), Quantum-dot Cellular Automata (QCA) and Carbon Nanotube Field Effect Transistor (CNFET) are introduced. Among the new technologies, CNFET has become center of attention due to similarities in electronic features in relation to MOSFET. A comparison made between CNFET with MOSFET technologies indicate that, power delay product (PDP) and power leakage can be less in nanotube transistors. Field effect transistor circuit's simulations are accomplished through HSPICE simulator. The simulation results indicate that this proposed Three-operand Carbon Nanotube Multiplier has a better performance in comparison with the three-operand multiplication done on computers nowadays, which we call it classical multiplier in this article.

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CNFET, Fast Multiplication, Multi-operand Carbon Nanotube Multiplier, Nanotechnology, Partial Product Reduction, Power Leakage

Короткий адрес: https://sciup.org/15014794

IDR: 15014794

Список литературы Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

  • R.Conway, and J.Nelson, "Improved RNS FIR filter architectures," Express Briefs, IEEE Transactions on Circuits and Systems II,vol. 51, no. 1, 2004, pp. 26-28.
  • A.Menezes, P. C. Oorschot, andS. A.Vanstone, Handbook of Applied Cryptography, 1996, CRC Press.
  • M. R.Reshadinezhad, and F. K.Samani, "A novel low complexity Combinational RNS multiplier using parallel prefix adder," International Journal of Computer Science Issues (IJCSI), vol. 10, 2013, no. 2.
  • B.Parhami, Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press, Inc., 2009.
  • G.Cho, Y. B.Kim, F.Lombardi, and M. Choi, "Performance evaluation of CNFET-based logic gates," Instrumentation and Measurement Technology Conference, IEEE, 2009, pp. 909-912.
  • S. J.Tans, A. R. Verschueren, and C.Dekker, "Room-temperature transistor based on a single carbon nanotube," Nature, vol. 393, no. 6680, 1998, pp. 49-52.
  • Y. B.Kim, Y. B.Kim, and F.Lombardi, "A novel design methodology to optimize the speed and power of the CNTFET circuits," 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, pp. 1130-1133.
  • M. H.Moaiyeri, R. F. Mirzaee, A.Doostaregan, K.Navi, and O. Hashemipour, "A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits," IET Computers & Digital Techniques, vol. 7, no. 4, 2013, pp. 167-181.
  • J. P.Deschamps, G. J. Bioul, and G. D.Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, John Wiley & Sons, 2006.
  • C. S.Wallace, "A suggestion for a fast multiplier," IEEE Transactions on Electronic Computers, 1964, pp. 14-17.
  • J. Y.Kang, and J. L.Gaudiot, "A fast and well-structured multiplier," Euromicro Symposium on Digital System Design, IEEE, 2004, pp. 508-515.
  • N.Itoh, Y. Naemura, H. Makino, Y. Nakase, T. Yoshihara, and Y. Horiba, "A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree," IEEE Journal of Solid-State Circuits, vol. 36, no. 2, 2001, pp. 249-257.
  • N. Azimi, H. Hoseini, A.Shahsavari, "Designing a novel ternary multiplier using CNTFET," International Journal of Modern Education and Computer Science (IJMECS), vol. 6, no. 11, 2014, pp. 45-51.
  • S. Mhaske, I. Ghosekar, P. Bhaskar, "Low-complexity wallace multiplier using energy-efficient full adder based on carbon nanotube technology," International Journal of Engineering Research and General Science, vol. 3, no. 2, 2015, pp. 1308-1313.
  • W. C.Yeh, and C. W.Jen, "High-speed Booth encoded parallel multiplier design," IEEE Transactions on Computers, vol. 49, no. 7, 2000.
  • J. Fadavi Ardekani, "M×N Booth encoded multiplier generator using optimized Wallace trees," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, 1993, pp. 120-125.
  • G.Jaberipur, and B.Parhami, "Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms," 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), IEEE, 2010, pp. 3-9.
  • J. N. M.Mori, M.Hirano, S. Tanaka, M.Noda, Y. Toyoshima, and K. Maeguchi, "A 10 ns 54×54 b parallel structured full array multiplier with 0.5 μm CMOS technology," IEEE Journal of Solid-State Circuits, vol. 26, no. 4, 1991, pp. 600-606.
  • H.Kobayashi, "A fast multi-operand multiplication scheme," Proceedings of the 7th Symposium on Computer Arithmetic, 1981, pp. 246-250.
  • R.McIlhenny, and M. D.Ercegovac, "On the implementation of a three-operand multiplier," ConferenceRecord of the Thirty-First Asilomar, IEEE, vol. 2, 1997, pp. 1168-1172.
  • M. R.Reshadinezhad, and K.Navi, "High-speed multiplier design using multi-operand multipliers," International Journal of Computer Science and Network, 2012.
  • K.Navi, R. E. S.Rad, M. H.Moaiyeri, and A. Momeni, "A low-voltage and energy-efficient full adder cell based on carbon nanotube technology," Nano-Micro Letters, vol. 2, no. 2, 2010, pp. 114-120.
  • M. R.Reshadinezhad, M. H.Moaiyeri, and K.Navi, "An energy-efficient full adder cell using CNFET technology," IEICE transactions on electronics, vol. 95, no. 4, 2012, pp. 744-751.
  • M. H.Moaiyeri, R. F.Mirzaee, K.Navi, and A.Momeni, "Design and analysis of a high-performance CNFET-based Full Adder," International Journal of Electronics, vol. 99, no. 1, 2012, pp. 113-130.
  • R. Martel, T. Schmidt, HR. Shea, T. Hertel, P. Avouris, "Single-and multi-wall carbon nanotube field-effect transistors," Applied Physics Letters, vol. 73, no. 17, 1998, pp. 2447-2449.
  • HT. Soh, CF. Quate, AF. Morpurgo, CM. Marcus, J. Kong, H. Dai, "Integrated nanotube circuits: Controlled growth and ohmic contacting of single-walled carbon nanotubes," Applied Physics Letters, , vol. 75, no. 5,1999, pp. 627-629.
  • C. Zhou, J. Kong,H. Dai, "Electrical measurements of individual semiconducting single-walled carbon nanotubes of various diameters," Applied Physics Letters, vol. 76, no. 12,2000, pp. 1597-1599.
  • M. H. Moaiyeri, R. F. Mirzaee, K. Navi,O. Hashemipour, "Efficient CNTFET-based ternary full adder cells for nanoelectronics," Nano-Micro Letters, vol. 3, no. 1,2011, pp. 43-50.
  • Stanford University, 2014. Stanford CNFET Model. [Online] Available at: https://nano.stanford.edu/stanford-cnfet-model[Accessed 27 9 2014]
  • J. Deng,HS. Wong, "A circuit-compatible SPICE model for enhancement mode carbon nanotube field effect transistors," International Conference onSimulation of Semiconductor Processes and Devices, 2006, pp. 166-169.
  • J. Deng,HS. Wong,"A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region," IEEE Transactions on Electron Devices, vol. 54, no. 12,2007, pp. 3186-3194.
  • J. Deng,HS. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking," IEEE Transactions onElectron Devices, vol. 54, no. 12, 2007, pp. 3195-3205.
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