Design of an arbiter for two systems accessing a single DDR3 memory on a reconfigurable platform
Автор: Arun S. Tigadi, Hansraj Guhilot
Журнал: International Journal of Information Engineering and Electronic Business @ijieeb
Статья в выпуске: 6 vol.10, 2018 года.
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The computer memory has been revolutionized in the last 25-30 years, in terms of both capacity and speed of execution. Along with this, even the logic controlling the memory has also become more and more complex and difficult to interface. Usually, memory subsystems will be designed to interact with a single system. Whenever we consider a two system is sharing a common memory, there comes the need for an Arbiter. The major difference between a memory arbiter and a processor scheduler is that the memory arbiter works at a much finer level of granularity. The time taken for the task execution may range from micro to milliseconds, while a RAM controller needs to serve the request in a few nanoseconds. Because of this reason the resource arbiters are usually designed and implemented in hardware rather than in software.
Arbiter, memory controller, FPGA(Field programmable gate Array), SDRAM (Synchronous DRAM)
Короткий адрес: https://sciup.org/15016152
IDR: 15016152 | DOI: 10.5815/ijieeb.2018.06.02
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