Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis

A low power Test Pattern Generator (TPG) designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors that are deployed on Circuit under Test (CUT) to slenderize the dynamic power consumption by CUT. The technique involved in generating low power test patterns is performed by increasing the correlativity between the successive vectors; the ambiguity in increasing the similarity between consecutive vectors is resolved by reducing the number of bit flips between successive test patterns. Upon deploying the low power test patterns at the inputs of CUT, slenderizes the switching activities inside CUT that in turn reduces its dynamic power consumption. The resulted low power test vectors are deployed on CUT to obtain fault coverage. The experimental results demonstrate significant power reduction by low power TPG than compared to standard LFSR.