Design of near threshold 10T- full subtractor circuit for energy efficient signal processing applications
Автор: M.Mahaboob Basha, K.Venkata Ramanaiah, P. Ramana Reddy
Журнал: International Journal of Image, Graphics and Signal Processing @ijigsp
Статья в выпуске: 12 vol.9, 2017 года.
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In recent years, near threshold computing is becoming a promising solution to achieve minimum energy consumption. In this paper, the Dynamic Threshold body MOS (DTMOS) technique is assessed in the context of 10T full subtractor circuit designed to operate in the near threshold region. The performance parameters – Energy, power, area, delay, and EDP were computed and compared with the conventional CMOS (C-CMOS) Full subtractor. The simulations were performed using cadence 90 nm technology with Ultra Low Voltage (ULV) of 0.3V. The results have been shown that the proposed 10T full subtractor circuit with DTMOS scheme achieves more than 18% savings in delay, 26% savings in energy consumption and 39% savings in EDP in comparison with the conventional CMOS configuration and other hybrid counterparts.
CMOS (Complementary Metal Oxide Semiconductor) logic, DTMOS (Dynamic Threshold body Metal Oxide Semiconductor) logic, Energy, full subtractor, Near Threshold, ULV (Ultra Low Voltage)
Короткий адрес: https://sciup.org/15015921
IDR: 15015921 | DOI: 10.5815/ijigsp.2017.12.03
Список литературы Design of near threshold 10T- full subtractor circuit for energy efficient signal processing applications
- Wang A, Benton.H.Calhoun, and A. Chandrakasan. subthreshold design for ultra low-power systems. 1st edition. Springer : 2006.
- Michael Hbner and Cristina Silvano. Near Threshold Computing: Technology, Methods and Applications. 1st edition. Springer: 2015.
- R. Dreslinski et al., “Near-threshold computing: Reclaiming Moore’s law through energy efficient integratedcircuits,”Proc.IEEE,no.2,pp. 253–266, Feb. 2010.
- Neil.H.Weste and David Harris. CMOS VLSI design- A circuits and systems perspective. 3rdEdition. Addison Wesley: 2004.
- Zimmermann R, Fichtner W. Low-power logic styles: CMOS versus pass-transistor logic. IEEE Journal of Solid-State Circuits, 1997, 32(7):1079-1090.
- Alioto M, Cataldo GD, Palumbo G. Mixed full adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal, 2007, 38(1):130-139.
- Shams AM, Darwish TK, Bayoumi MA. Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Transactions on VLSI Systems, 2002, 10(1):20-29.
- M.Mahaboob Basha, K.Venkata Ramanaiah, P. Ramana Reddy. Low Area-High speed- Energy efficient one bit full subtractor with MTCMOS. International Journal of Applied Engineering Research, 2015, 10(11): 27593-27604
- Assaderaghi F, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation. IEDM Tech. Dig., 1994, 809–812.
- Kishore.S, Sakthivel R. Low power realization of subthreshold digital logic circuits using Body bias Technique. Indian Journal of Science and Technology. 2016, 9(5),1-5.
- Shih-Fen Huang et.al, Scalability and biasing strategy for CMOS with active well bias. 2001 Symposium on VLSI Technology, 107-108.
- USN Rao, B Raja Ramesh. Adaptive Signal Processing for Improvement of Convergence Characteristics of FIR Filter. IJIGSP, 2013, 5(12):18-25.
- Zhanfeng Zhang,Liyuan Sheng,Wenming Jiang,Shuai Tong,Hua Cao. A New Adder Theory Based on Half Adder and Implementation in CMOS Gates. IJIGSP, 2010, 2(2): 11-17.
- Abdul Sajid, Ahmad Nafees, Saifur Rahman. Design and Implementation of Low Power 8-bit Carry-look Ahead Adder Using Static CMOS Logic and Adiabatic Logic. IJITCS, 2013, 5(11):78-92.
- Shekoofeh Moghimi, Mohammad R. Reshadinezhad. A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics. IJMECS, 2015, 7(11),:28-34.
