Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency

Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.