Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2
Автор: Hassen Mestiri, Fatma Kahri, Belgacem Bouallegue, Mohsen Machhout
Журнал: International Journal of Computer Network and Information Security(IJCNIS) @ijcnis
Статья в выпуске: 1 vol.7, 2014 года.
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The Hash function has been studied by designers with the goal to improve its performances in terms of area, frequency and throughput. The Hash function is used in many embedded systems to provide security. It is become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and SHA-512 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieves good performance in term of area, frequency and throughput.
Security, SHA-256, SHA-512, FPGA Implementation
Короткий адрес: https://sciup.org/15011373
IDR: 15011373
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