FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Автор: Shujaat Khan, M. Sohail Ibrahim, Mansoor Ebrahim, Haseeb Amjad

Журнал: International Journal of Computer Network and Information Security(IJCNIS) @ijcnis

Статья в выпуске: 12 vol.7, 2015 года.

Бесплатный доступ

Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers, a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently proposed Secure Force (SF) shows good results in terms of resource utilization compared to older ciphers. SF appears as a promising choice for power and resource constrained secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a full loop-unroll implementation of SF-64 on FPGA. This work provides hardware characteristics of SF along with implementation results that are optimal in terms of throughput, latency, power utilization and area efficiency.

Еще

SF (Secure Force), FPGA, ASIC, WSN (Wireless Sensor Networks), security algorithms, Hardware implementation

Короткий адрес: https://sciup.org/15011483

IDR: 15011483

Список литературы FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

  • Ebrahim, Mansoor, and Chai Wai Chong. "Secure Force: A low-complexity cryptographic algorithm for Wireless Sensor Network (WSN)." Control System, Computing and Engineering (ICCSCE), 2013 IEEE International Conference on. IEEE, 2013.
  • Elbirt, Adam J., et al. "An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 9.4 (2001): 545-557.
  • Standaert, Francois-Xavier, et al. "Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs." Cryptographic Hardware and Embedded Systems-CHES 2003. Springer Berlin Heidelberg, 2003. 334-350.
  • Ji, Bing, Liejun Wang, and Qinghua Yang. "New Version of AES-ECC Encryption System Based on FPGA in WSNs." Journal of Software Engineering 9.1 (2015): 87-95.
  • Chodowiec, Paweł, and Kris Gaj. "Very compact FPGA implementation of the AES algorithm." Cryptographic Hardware and Embedded Systems-CHES 2003. Springer Berlin Heidelberg, 2003. 319-333.
  • Zambreno, Joseph, David Nguyen, and Alok Choudhary. "Exploring area/delay tradeoffs in an AES FPGA implementation." Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. 575-585.
  • E. Biham and A. Shamir, "Differential cryptanalysis of data encryption standard". Berlin, Germany: Springer-Verlag, 1993.
  • Khan, Shujaat, Mansoor Ebrahim, and Kafeel Ahmed Khan. "Performance Evaluation of Secure Force Symmetric Key Algorithm." (2015).
  • Llamocca, Daniel, Marios Pattichis, and G. Alonzo Vera. "Partial reconfigurable FIR filtering system using distributed arithmetic." International Journal of Reconfigurable Computing 2010 (2010): 4.
  • Gaj, Kris, Ekawat Homsirikamol, and Marcin Rogawski. "Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs." Cryptographic Hardware and Embedded Systems, CHES 2010. Springer Berlin Heidelberg, 2010. 264-278.
  • Huang, Chi-Wu, et al. "Compact FPGA implementation of 32-bits AES algorithm using Block RAM." TENCON 2007-2007 IEEE Region 10 Conference. IEEE, 2007.
  • Chang, Chi-Jeng, et al. "High throughput 32-bit AES implementation in FPGA." Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on. IEEE, 2008.
  • Good, Tim, and Mohammed Benaissa. "AES on FPGA from the fastest to the smallest." Cryptographic Hardware and Embedded Systems–CHES 2005. Springer Berlin Heidelberg, 2005. 427-440.
  • Bulens, Philippe, et al. "Implementation of the AES-128 on Virtex-5 FPGAs." Progress in Cryptology–AFRICACRYPT 2008. Springer Berlin Heidelberg, 2008. 16-26.
  • Kong, Jia Hao, Li-Minn Ang, and Kah Phooi Seng. "A comprehensive survey of modern symmetric cryptographic solutions for resource constrained environments." Journal of Network and Computer Applications 49 (2015): 15-50.
  • Altera ® Cyclone II Architecture. Website: http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf.
  • M. Ebrahim, S. Khan and U.B. Khalid," Symmetric algorithm survey: a comparative analysis". International Journal of Computer Applications 61(20), January 2013, pp. 12-19. USA
  • Ebrahim, Mansoor, Shujaat Khan, and Syed Sheraz Ul Hasan Mohani. "Peer-to-Peer Network Simulators: an Analytical Review." Asian Journal of Engineering Science and Technology (2012).
  • Ebrahim, Mansoor, Shujaat Khan, and UmerBin Khalid. "Security Risk Analysis in Peer 2 Peer System; An Approach towards Surmounting Security Challenges." Asian Journal of Engineering Science and Technology (2012).
  • Borkar, Atul M., R. V. Kshirsagar, and M. V. Vyawahare. "FPGA implementation of AES algorithm." Electronics Computer Technology (ICECT), 2011 3rd International Conference on. Vol. 3. IEEE, 2011.
  • Šćekić, Ognjen., Ognjen. "FPGA Comparative Analysis."
  • Dynamic Power Reduction in Flash FPGAs. AC323, Microsemi.
  • R. Chandramouli, S. Bapatla, and K. P. Subbalakshmi, "Battery power-aware encryption", ACM Transactions on Information and System Security, Vol. 9, No. 2, May 2006, pp. 162–
  • Rashidi, Bahram, and Bahman Rashidi. "Implementation of an optimized and pipelined combinational logic rijndael S-Box on FPGA." International Journal of Computer Network and Information Security (IJCNIS) 5.1 (2013): 41.
  • Rashidi, Bahram, and Bahman Rashidi. "FPGA Based A New Low Power and Self-Timed AES 128-bit Encryption Algorithm for Encryption Audio Signal."International Journal of Computer Network and Information Security (IJCNIS)5.2 (2013): 10.
  • Zheng, Jingli, Zhengbing Hu, and Chuiwei Lu. "A Light-weight Symmetric Encryption Algorithm Based on Feistel Cryptosystem Structure." International Journal of Computer Network and Information Security (IJCNIS) 7.1 (2014): 16.
  • Mestiri, Hassen, et al. "Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2." International Journal of Computer Network and Information Security (IJCNIS) 7.1 (2014): 9.
Еще
Статья научная