Hardware implementation of the unit of the GNSS consumer

Navigational equipment is currently used to solve a variety of tasks, such as providing civil and special aviation, navigating, surveying and mapping, Internet devices and unmanned vehicles perfomance. The level of technological development of digital signal processing devices at first glance removes the need for deep study of computational algorithms, but this is only at first glance. As a result of expanding the scope of navigation tools, there is a need to increase the working channels, increase the dynamic range of the processed signals, and also improve the reconfiguration capabilities of signal processing devices. Any synthesized computational algorithm that can be described in hardware description languages, such as VHDL and Verilog, consists of summation operations and a shift operation of the register. There are several basic architectures of adders, each of which has the advantage of either speed of operation or simplicity of implementation. The development of computational architectures working at frequencies of 100 - 200 MHz requires pipeline calculations. Despite the fact that the pipeline architecture has large overheads for equalizing the delays of the computational blocks, its use is justified when processing and converting signals while solving the navigation task. The architecture of hardware computational blocks for constructing navigation equipment for the GLONASS / GPS consumer is considered in the article. The possible ways of increasing the efficiency of some architectures when implementing them on the basis of programmable gate arrays (FPGA) are given.