Interconnect network on chip topology in multi-core processors: a comparative study
Автор: Manju Khari, Raghvendra Kumar, Dac-Nhuong Le, Jyotir Moy Chatterjee
Журнал: International Journal of Computer Network and Information Security @ijcnis
Статья в выпуске: 11 vol.9, 2017 года.
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A variety of technologies in recent years have been developed in designing on-chip networks with the multicore system. In this endeavor, network interfaces mainly differ in the way a network physically connects to a multicore system along with the data path. Semantic substances of communication for a multicore system are transmitted as data packets. Thus, whenever a communication is made from a network, it is first segmented into sub-packets and then into fixed-length bits for flow control digits. To measure required space, energy & latency overheads for the implementation of various interconnection topologies we will be using multi2sim simulator tool that will act as research bed to experiment various tradeoffs between performance and power, and between performance and area requires analysis for further possible optimizations.
Topology, Multicore Processor, Multi2sim Simulator, Super Scalar, Pipeline
Короткий адрес: https://sciup.org/15015554
IDR: 15015554 | DOI: 10.5815/ijcnis.2017.11.06
Список литературы Interconnect network on chip topology in multi-core processors: a comparative study
- Schauer, B. (2008). Multicore processors - a necessity. ProQuest discovery guides, 1-14.
- Mukherjee, S. S., Bannon, P., Lang, S., Spink, A., & Webb, D. (2002). The Alpha 21364 network architecture. IEEE micro, 22(1), 26-35.
- Ubal, R., Sahuquillo, J., Petit, S., & Lopez, P. (2007, October). Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. In Sbac-Pad (pp.62-68).
- Owens, J. D., Dally, W. J., Ho, R., Jayasimha, D. N., Keckler, S. W., &Peh, L. S. (2007). Research challenges for on-chip interconnection networks. IEEE micro, 27(5), 96-108.
- Barr, K. C. (2006). Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots (Doctoral dissertation, Massachusetts Institute of Technology).
- Nanehkaran, Y. A., & Ahmadi, S. B. B. (2013). The Challenges of Multi-Core Processor. International Journal of Advancements in Research & Technology, 2(6), 36-39.
- McLean, R. A. R. A. (1984). Applied factorial and fractional designs (No. 04; QA279, M2.).
- Burger, D., & Austin, T. M. (1997). The SimpleScalar tool set, version 2.0. ACM SIGARCH computer architecture news, 25(3), 13-25.
- Madoń, D., Sanchez, E., &Monnier, S. (1999, August). A study of a simultaneous multithreaded processor implementation. In European Conference on Parallel Processing (pp. 716-726). Springer, Berlin, Heidelberg.
- Sharkey, J., Ponomarev, D., &Ghose, K. (2005). M-sim: a flexible, multithreaded architectural simulation environment. Techenical report, Department of Computer Science, State University of New York at Binghamton.
- Moudgill, M., Bose, P., & Moreno, J. H. (1999, February). Validation of Turandot, a fast processor model for microarchitecture exploration. In Performance, Computing and Communications Conference, 1999 IEEE International (pp. 451-457). IEEE.
- Moudgill, M., Wellman, J. D., & Moreno, J. H. (1999). Environment for PowerPC microarchitecture exploration. IEEE Micro, 19(3), 15-25.
- D. Brooks, P. Bose, V. Srinivasan, M. Gschwind, and M. Rosenfield P. Emma. Microarchitecutre-Level Power-Performance Analysis: The Power Timer Approach. IBM J. Research and Development, 47(5/6), 2003.
- Lee, B., & Brooks, D. (2005). Effects of pipeline complexity on SMT/CMP power-performance efficiency. Power, 106, 1.
- Xu, Z. (2008). Migration from electronics to photonics in multicore processor(Doctoral dissertation, Massachusetts Institute of Technology).
- Shen, J. P., &Lipasti, M. H. (2013). Modern processor design: fundamentals of superscalar processors. Waveland Press.
- Umbarkar, A. J., Rothe, N. M., &Sathe, A. S. (2015). OpenMP teaching-learning based optimization algorithm over multi-core system. International Journal of Intelligent Systems and Applications, 7(7), 57.
- Khan, Z. A., Siddiqui, J., &Samad, A. (2015). Linear crossed cube (LCQ): A new interconnection network topology for massively parallel system. International Journal of Computer Network and Information Security, 7(3), 18.
- Dehghani, F., &Darooei, S. (2016). A Novel Architecture for Adaptive Traffic Control in Network on Chip using Code Division Multiple Access Technique. International Journal of Computer Network and Information Security, 8(8), 20.
- Nazir, L., & Mir, R. N. (2016). Realization of Efficient High Throughput Buffering Policies for Network on Chip Router. International Journal of Computer Network and Information Security, 8(7), 61.
- Rustogi, S., Sharma, M., &Morwal, S. (2017). Improved Parallel Apriori Algorithm for Multi-cores. International Journal of Information Technology and Computer Science (IJITCS), 9(4), 18.
- Joseph, P. M., Rajan, J., Kuriakose, K. K., & Murty, S. S. (2013). Exploiting SIMD Instructions in Modern Microprocessors to Optimize the Performance of Stream Ciphers. International Journal of Computer Network and Information Security, 5(6), 56.
- Le, D. N. (2013). Optimizing the cMTS to Improve Quality of Service in Next Generation Networks based on ACO Algorithm. International Journal of Computer Network and Information Security, 5(4), 25.
- Basmadjian, R., & de Meer, H. (2012, May). Evaluating and modeling power consumption of multi-core processors. In Proceedings of the 3rd International Conference on Future Energy Systems: Where Energy, Computing and Communication Meet (p. 12). ACM.
- M2S Guide 4.2, The Multi2Sim Simulation Framework, www.multi2sim.org.
