Use of statistical distributions in verification of digital blocks

The article discusses the main aspects of using distribution constraints in the SystemVerilog hardware description language. The author explains how to specify probability distribution of values within a test by means of constraints, thanks to which test flexibility and verification efficiency can be significantly increased. The paper describes in detail the syntax and semantics of basic distributional constraints and gives examples of their application in modelling and testing. At the same time, the results of randomisation when combining different types of constraints are investigated, and the relationship between the constraints and the resulting probability distribution function is derived. The paper will be useful to verification engineers seeking to improve the quality and speed of verification.