Modified multiply and accumulate unit to increasing of digital filters performance

This paper proposes a modified architecture of the multiply and accumulate units and their application for increasing the performance of digital filters with a finite impulse response. The paper provides a theoretical analysis of the proposed modified multipliers and implements hardware simulation.The theoretical analysis has shown that replacing traditional multiply and accumulate units by modified ones as the basis for the implementation of digital filters can theoretically reduce the filtering time to 29 %. Hardware simulation has shown that modified multiply and accumulate units increase the performance of digital filters by up to 11 % compared to digital filters using traditional multiply and accumulate units by increasing hardware costs. The results of this research can be used in the theory of digital signal processing to solve practical problems, such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization, etc.