Novel design of 32-bit asynchronous (RISC) microprocessor & its implementation on FPGA
Автор: Archana Rani, Naresh Grover
Журнал: International Journal of Information Engineering and Electronic Business @ijieeb
Статья в выпуске: 1 vol.10, 2018 года.
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As the efficiency and power consumption plays an important role in electronic system design, an asynchronous design is used to reduce such challenges faced in synchronous architectures. The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper deals with the novel design and implementation of such type of asynchronous microprocessor by using VHDL on Xilinx ISE tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.
Asynchronous design, Processor, VHDL, MIPS, Synthesis & Simulation, Instruction data path, EDA Tools
Короткий адрес: https://sciup.org/15016121
IDR: 15016121 | DOI: 10.5815/ijieeb.2018.01.06
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