Evaluation of FPGA's self-timed LUT complexity

Currently, the so-called programmable logic integrated circuits (including FPGAs) are widely applied. They usually use synchronized information processing based on a clock generator, with the clock frequency calculated for the worst case possible, for the longest transition process. Asynchronous FPGAs work according to real delays of elements and devices; however, the synthesis of asynchronous circuits is much more complicated than that of synchronous ones. One of the types of asynchronous circuits are the so-called self-timed (ST) circuits (STC). The article discusses the proposed logical elements for ST FPGA and provides the obtained estimates of complexity.