Reconfigurable parralel multiple in the Galois fields in combination logic
Автор: Zubov Timur A., Sukhotin Vitaly V., Khnykin Anton V., Mishurov Andrey V., Gorchakovsky Alexander A.
Журнал: Журнал Сибирского федерального университета. Серия: Техника и технологии @technologies-sfu
Статья в выпуске: 7 т.12, 2019 года.
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The concept of “multiplier” in Galois fields, which are widely used in cryptography and noise-resistant coding, is considered. The architecture of a parallel multiplier for the Galois fields is analyzed. Reconfigurable multiplier is constructed. It is shown that the use of this type of multiplier will significantly reduce the number of logic gates.
Multiplier, galois fields, combinational logic, reconfigurable module, bose chaudhuri hocquenghem codes
Короткий адрес: https://sciup.org/146281394
IDR: 146281394 | DOI: 10.17516/1999-494X-0180
