The system of software-driven verification of network IP-cores in a reference system-on-chip

The article presents the application of network Intellectual Property cores (IP cores) software-driven verification method for network infrastructure devices in the system-on-chip microprocessor (SoC) used as verification environ- ment. The SoC used for verification is a reference system since it consists of previously fully verified and approved IP cores which interact in this system correctly and accurately. Software of a reference system generates test inputs and processes responses to them which are received from a verified device. Conclusions of executed or unexecuted tests are generated on the basis of the expected results. A set of expected results of input action is a reference model of a verified IP core. General architecture of a verification system of a network device IP core has a form of a classic test loop. The vari- ants of verification architecture given depend on the type of a verified network device: an individual network codec, a network protocol controller or a network switch. The presented architectures show the simplicity of software-driven verification. The test environment naturally results from the reference SoC model and test software developed in such high-level programming language as C/C++. When the software-driven verification of an IP core takes place in reference SoC environment, the test software con- sists of two types of tests: directed tests and restricted-random tests. Successive use of both the given types of tests and typical scenarios of network devices interaction which include request-reply packages transmission between network nodes provides high coverage of a verified IP core with test situations. To check fault tolerance function it is supposed to use the scenarios of network devices interaction in conditions of possible faults made by predetermined introducing of errors into packages transmitted over the network connections. Program tests which are developed and proved during the IP core model verification are completely ready to be used in hardware SoC prototype including the given IP core in the programmable logic device. The presented approach to functional verification was used for IP cores testing in SpaceWire network infrastruc- ture: a fault tolerance codec, a RMAP protocol controller and a routing switch.