A Noise and Mismatches of Delay Cells and Their Effects on DLLs
Автор: Mohammad Gholami, Gholamreza Ardeshir, Hossein Miar-Naimi
Журнал: International Journal of Intelligent Systems and Applications(IJISA) @ijisa
Статья в выпуске: 5 vol.6, 2014 года.
Бесплатный доступ
Jitter is one of the most important parameters in design of delay locked loop (DLL) based frequency synthesizer. In this paper noise and mismatches of conventional delay cells which are mainly used in the DLLs architecture are introduced completely. First, time domain equations related to noise and mismatches of conventional delay cells are reported. Then, these equations are used to calculate jitter of DLL due to mismatch and noise of delay cells. At last closed form equations are obtained which can be used in the designing of low jitter DLLs. To validate these equations, a conventional DLL is designed in TSMC 0.18um CMOS Technology.
Mismatches, Noise, Phase Errors, Jitter, DLL, Delay Locked Loo
Короткий адрес: https://sciup.org/15010555
IDR: 15010555
Список литературы A Noise and Mismatches of Delay Cells and Their Effects on DLLs
- M. Gholami, Gh. Ardeshir and H. Ghonoodi, “A novel architecture for low voltage-low power DLL-based frequency multipliers”, IEICE Electron. Express, Vol. 8, No. 11, pp.859-865, (2011).
- Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Suki Kim; , "A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.19, no.9, pp.1718-1722, Sept. 2011.
- J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bangbang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, pp. 1571–1580, Sep. 2004.
- Oh, K.-I.; Kim, L.-S.; Park, K.-I.; Jun, Y.-H.; Kim, K.; , "Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface," Electronics Letters , vol.44, no.19, pp.1121-1123, September 11 2008.
- C. Kim, I.-C. Hwang, and S.-M. Kang, “A low-power small-area 7.28-ps-jitter 1-GHz DLL-based clock generator,” IEEE J. Solid-State Circuits, vol. 37, pp. 1414–1420, Dec. 2002.
- Razavi B., "RF Microelectronics", Second Edition, PRENTICE HALL, 2012.
- Gholami, M.; Fallah, M., "Increasing frequency of ring oscillators by using negative capacitors," Electronics Letters , vol.48, no.18, pp.1109,1110, August 30 2012. DOI: 10.1049/el.2012.2261.
- Gholami, Mohammad and Rahimpour, Hamid., "Design and analysis of negative capacitor by using MOSFETs," International Journal of Electronics, pp.1,11, 2013. DOI: 10.1080/00207217.2013. 817023.
- Rahimpour, Hamid, Mohammad Gholami, Hossein Miar-Naimi, and Gholamreza Ardeshir. "All digital fast lock DLL-based frequency multiplier." Analog Integrated Circuits and Signal Processing (2013): 1-8. DOI: 10.1007/s10470-013-0205-9.
- Gholami, Mohammad, Hamid Rahimpour, Gholamreza Ardeshir, and Hossein Miar‐Naimi. "A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers." International Journal of Circuit Theory and Applications (2013). DOI: 10.1002/cta.1958
- Gholami, Mohammad, Hamid Rahimpour, Gholamreza Ardeshir, and Hossein MiarNaimi. "Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers." Institution of Engineering and Technology (2013). DOI: 10.1049/iet-cds.2013.0169
- Lee, M.-J.E.; Dally, W.J.; Greer, T.; Hiok-Tiaq Ng; Farjad-rad, R.; Poulton, J.; Senthinathan, R., "Jitter transfer characteristics of delay-locked loops - theories and design techniques," Solid-State Circuits, IEEE Journal of , vol.38, no.4, pp.614,621, Apr 2003.
- Won-Joo Yun; Hyun-Woo Lee; Shin, Dongsuk; Suki Kim, "A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.19, no.9, pp.1718,1722, Sept. 2011.
- Wu Gao; Deyuan Gao; Brasse, D.; Hu-Guo, C.; Yann Hu, "Precise Multiphase Clock Generation Using Low-Jitter Delay-Locked Loop Techniques for Positron Emission Tomography Imaging," Nuclear Science, IEEE Transactions on , vol.57, no.3, pp.1063,1070, June 2010
- Weigandt, T.C.; Beomsup Kim; Gray, P.R.; , "Analysis of timing jitter in CMOS ring oscillators," Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on , vol.4, no., pp.27-30 vol.4, 30 May-2 Jun 1994.
- Gholami M.; "A Novel Low Power Architecture for DLL-Based Frequency Synthesizers," Circuits, Systems, and Signal Processing: Volume 32, Issue 2 (2013), Page 781-801. DOI: 10.1007/s00034-012-9488-9.
