The analysis of approaches for the synthesis of networks-on-chip by using regular topologies

The article gives a review of existing methods of networks-on-chip design, based on the approach, in which the projection of the characteristic tasks graph is performed on a given regular topology. The general problem of the synthesis of networks-on-chip is characterized. The network topology can be foreknown (usually a regular topology) or selected in accordance with the tasks that will be performed by the network-on-chip. The first method of synthesis of networks-on-chip is widespread among the developers due to its relative simplicity and obviousness and presented in a variety of implementations, which are reviewed in this article. The advantages and disadvantages of this approach, the effect achieved by its application to various implementations of networks-on-chip and the way of its improvement, which consists in extension of the scope of solutions for regular network topologies on the predetermined irregular topologies with better characteristics are offered.