Automatic mapping programs onto a processor with an FPGA accelerator
Автор: Dubrov D.V., Roshal A.S., Steinberg B.Ya., Steinberg R.B.
Рубрика: Краткие сообщения
Статья в выпуске: 2 т.3, 2014 года.
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A problem of automatic high level program mapping onto a CPU with an FPGA accelerator is considered in this work. For such a mapping an HDL code generator from a parallelizing system’sinternal representation is being developed and used.
High-level synthesis, parallelizing compiler, vhdl, social network analysis, information retrieval, data mining, expert finding, popularity analysispeline computing, fpga
Короткий адрес: https://sciup.org/147160528
IDR: 147160528
Краткое сообщение
