Design and Implementation of Low Power 8-bit Carry-look Ahead Adder Using Static CMOS Logic and Adiabatic Logic
Автор: Abdul Sajid, Ahmad Nafees, Saifur Rahman
Журнал: International Journal of Information Technology and Computer Science(IJITCS) @ijitcs
Статья в выпуске: 11 Vol. 5, 2013 года.
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Addition forms the basic structure for many processing operations like counting, multiplication, filtering etc. Adder circuits that add two binary numbers are of great interest for many designers. The simplest approach to design an adder is to implement gates to yield the required logic function. Carry-look ahead adder is a major functional block in arithmetic logic unit due to its high speed operation. The arithmetic logic unit has been widely used in microprocessor systems and mostly in processing modules of embedded systems. Therefore, it is of interest to study the functional behavior and power consumption carry-look ahead adder. In this project, the adder is implemented using 180 nm CMOS technology on bulk substrate. Two logic families i.e. static CMOS and adiabatic logic have been analyzed and implemented to study the transient characteristics of the adder. Finally the power consumption is estimated and compared. From the results it has been found that the static CMOS logic offers low delay whereas the adiabatic logic consumes low power.
Adiabatic Logic, GATE, Power Analysis, CMOS
Короткий адрес: https://sciup.org/15011994
IDR: 15011994
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