Design of 12B/14B: A Novel SERDES Encoding Technique

In satellite systems, large amount of high speed data is required to be transmitted from one system to another. Conventional parallel data transmission requires a large number of cables/interface-packages and results in large weight and volume. Parallel interface in a typical future camera system requires >8000 cables between camera electronics and data handling system. In addition, with increase in transmission rate, problems associated with crosstalk become more critical. One possible solution identified is serial interface, also termed as SERDES (SERializer/DESerializer) interface. A typical SERDES interface comprises of encoder/decoder, PLL, timing-control and multiplexer/de-multiplexer. Encoding of serial data solves high speed serial data transmission problems by incorporating clock embedding, DC balancing, sync info insertion and error detection. DC balancing also solves the issue of Inter-Symbol Interference (ISI). Available SERDES interface devices have limitations like poor reduction factor, no clock embedding or non-availability of space qualified part. Hence, an attempt is made to understand and implement SERDES encoder/decoder with a goal of indigenous SERDES ASIC development. Due to 12-bit input interface, a novel 12B/14B encoding technique is designed and developed. The developed technique preserves many good properties widely used 8B/10B encoding technique. FPGA simulation results achieved >50MSPS parallel rate which will lead to >700 Mpbs serial rate. Developed technique is very efficient and suitable for onboard implementation.