A formal system of getting redundant self-timed CMOS-structures

The author suggests a combined reservation of transistor configurations parrying failures of some transistors that result from exposure to radiation and other negative factors. However, such redundancy is not always possible due to the limitations of Mead and Conway concerning the number of series-connected transistors. A formal system to obtain a fault-tolerant CMOS self-timed circuits taking into account the predetermined limit is proposed.