Simulation of a tripled majority voter by quartus prime state machine

A triple majority element based on a full adder in the Quartus Prime State Machine is investigated to create highly reliable FPGA-based digital automata. For this purpose, two new groups of inputs are added to the previously developed automaton graph. Modeling the failure of one of the three majorities is performed by specifying the corresponding constant in one of the three input groups. The performance indicators of the developed device are evaluated.