NoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology
Автор: Xingang Ju, Liang Yang
Журнал: International Journal of Information Technology and Computer Science(IJITCS) @ijitcs
Статья в выпуске: 4 Vol. 3, 2011 года.
Бесплатный доступ
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, it introduces the basic concept and architecture of the NoC, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding, routing algorithm and node degree routing direction are designed. Thirdly, the programming and simulation of 2×4 NoC interconnection architecture are designed, and it achieves uninterrupted operation. The result shows the correctness of the interconnection architecture design. Finally, it chooses XC4VSX55-12ff1148 of vertext 4 to synthesize, the maximum frequency can up to 268 MHz, which provides foundation of subsequent research and application.
Network on Chip, On-chip communication, topology, routing node, routing algorithm, uninterrupted operation
Короткий адрес: https://sciup.org/15011635
IDR: 15011635
Список литературы NoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology
- Goossens K. A Ethereal Network on Chip: Concepts, Architectures and Implementations[J]. IEEE Design & Test of Computers, 2005, 22(5).
- Vivek Kumar Sehgal, Durg Singh Chauhan. State Observer Controller Design for Packets Flow Control in Networks-on-Chip. IBM Journal of Supercomputer, 2009.
- Tobias Bjerregaard and Shankar Mahadevan. A Survey of Research and Practices of Network-on-Chip. ACM Computing Surveys, 2006, 38: 1-51.
- Shuai Ding, Nin Wu, et al. The Research on System Level Modeling of Router for Network on Chip[J]. Microelectronics & Computer, 2009,26(1): 45-51.
- Yan Pan, Prabhat Kumar, John Kim, et al. Firefly: Illuminating Future Network-on-Chip with Nanophotonics. ISCA’09, 2009: 429-440.
- M. Mirza, S. Koohi, S. Hessabi,et al. An Empirical Investigation of Mesh and Torus NoC Topologies under Different Routing Algorithms and Traffic Models[C].the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools 2007:19-26.
- Duato, J., Yalamanchili, S., and Ni, L. Interconnection Networks: An Engineering Approach. Morgan Kaufmann. 2003.
- L. M. Ni and P. R. Mckinley. Wormhole Routing Techniques for Directly Connected Multicomputer Systems. ACM Computer Surveys, 1998, 26(5): 12-23.
- Chang Wu. The Research of Architecture and Key Communication Technology in Network on Chip [D]. xi’an: XiDian university, 2005.
- P P Pande, C Grecu, M Jones, et al. Performance Evaluation and Design Trade-offs for Network-on-Chip Interconnect Architectures. IEEE Transactions on Computers. August, 2005, 54(8): 1025-1040.
- E Bolotin, I Cidon, R Ginosar, et al. QNoC: QoS Architecture and Design Process for Network on Chip. J. Syst. Architecture: Euromicro J.Feb 2004, 50: 105-128.
