Performance analysis of LT codec architecture using different processor templates
Автор: S. M. Shamsul Alam
Журнал: International Journal of Information Technology and Computer Science @ijitcs
Статья в выпуске: 8 Vol. 11, 2019 года.
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Luby Transform (LT) code plays a vital role in binary erasure channel. This paper portrays the design techniques for implementation of LT codec using application specific instruction set processor (ASIP) design tools. In ASIP design, a common approach to increase the performance of processors is to boost the number of concurrent operations. Therefore, optimizations like strategy of input design, processor and compiler architecture are very useful phenomenon to enhance the performance of the application specific processor. Using Tensilica and OpenRISC processor design tools, this paper shows the response of LT codec architectures in terms of cycle counts and simulating time. Result shows that, the simulation speed of Tensilica is very high compared to the OpenRisc tool. Among different configurations of Tensilica tool, proposed ConnXD2 design took 1 M cycles per second and 135.66 ms to execute LT codec processor and XRC_D2MR configuration consumed only 9 iterations for successful decoding of LT encoded signal. Besides this, OpenRisc tool took 142K cycles and 6ms for executing LT encoder.
Luby Transform Code, processor design tools, cycle count, Simulation Speed, Custom Architecture
Короткий адрес: https://sciup.org/15016380
IDR: 15016380 | DOI: 10.5815/ijitcs.2019.08.06
Список литературы Performance analysis of LT codec architecture using different processor templates
- D. Liu, “Embedded DSP Processor Design: Application Specific Instruction Set Processor,” M.K. Publishers, Elsevier, pp. 20-200, 2007.
- P. Radosavljevic, “Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures,” Master’s Thesis, Rice University, Texas 2004.
- O. Esko, “ASIP Integration and Verification flow for FPGA,” Master’s Thesis, Tampere University of Technology, Tampare Finland, may 2011.
- S. Alam, and G. Choi, “Design and Implementation of LT Codec Architecture with Optimized Degree Distribution”, IEICE Electronics Express, Vol. 10, No. 12, doi: 10.1587/elex. 10.20130340, June 2013.
- TTA-based Co-design Environment v1.5. User Manual, Tampere University of Technology, Finland 2006.
- S. Alam, and G. Choi, “Design and Implementation of a Novel LT Codec Architecture on TTA Based Codesign Environment”, IEICE Electronics Express, Vol. 13, No. 13, pp.20160298, doi: elex.13.20160298, 2016.
- Tensilica Product, “Xtensa 7,” Product Brief.
- Tensilica Product, “ConnX D2 DSP Engine,” 2012 , http://www.tensilica.com/uploads/pdf/connx_d2_pb.pdf.
- D. Lampret, “OpenRISC 1000 Architecture Manual,” OpenCores (2012).
- K. Anantha Ganesh Karikar, “Automatic Verification of Microprocessor designs using Random Simulation,” Master’s thesis, Uppsala University, Sweden 2012.
- T. D. Nguyen, L. L. Yang, L. Hanzo, “Systematic Luby Transform Codes and Their Soft Decoding”, IEEE Workshop on Signal Processing Systems, doi: 10.1109/SIPS.2007.4387519, Chaina, 2007.
- H. Hussien, K.Shehata, S. Ramly, and N. Tawfik,” Design of a Merged Algorithm for Luby Transform Decoder”, International Journal of Computer and Communication Engineering, Vol. 1, No. 3, September 2012.
- T. D. Nguyen, L. L. Yang, S. X. Ng and L. Hanzo, “An Optimal Degree Distribution Design and a Conditional Random Integer Generator for the Systematic Luby Transform Coded Wireless Internet”, IEEE Wireless Communications and Networking Conference, DOI: 10.1109/WCNC.2008.48, USA, 2008.
- C. Albayrak, C. Sımsek, K. Türk, “Sign alterations of LLR values based early termination method for LT BP decoder”, 25th Signal Processing and Communications Applications Conference (SIU), doi: 10.1109/SIU.2017.7960434, Turkey, 2017.
- J. He, I. Hussain, Y. Li, M. Juntti, and T. Matsumoto, “Distributed LT Codes With Improved Error Floor Performance”, IEEE Access, doi: 10.1109/ACCESS.2018.2890452, Vol. 7, 2019.
- K. Zhang, X. Huang, and Chen Shen, “Soft decoder architecture of LT codes”, IEEE Workshop on Signal Processing Systems, doi:10.1109/SIPS.2008.4671764, 2008.
