Преобразование последовательной программы в параллельно-конвейерную форму для многокристальных реконфигурируемых вычислительных систем

Transforming a Sequential Program into a Parallel Pipeline Form for Multi-Chip Reconfigurable Computing Systems

Multi-chip reconfigurable computing systems (RCS) based on field-programmable gate arrays (FPGAs) require novel design tools capable of creating and scaling parallel pipelined programs with automatic dataflow synchronization. Such scaling tools should automatically synthesize efficient computational organizations—such as pipeline-within-pipeline and macropipeline architectures-without relying on specialized compiler directives. Previously, these forms could only be implemented manually by hardware engineers. This paper presents developed transformation techniques that convert sequential programs into a parallel pipelined form. This representation supports efficient computational structures and can be adapted to various RCS architectures and configurations without any changes to the source code. The resource-independent parallel pipelined program representation ensures flexible and coordinated scaling of both the computational fabric and the data streams, depending on the available computational resources across a multi-FPGA system. The performance of parallel pipelined programs generated by the Teseus framework is compared against the widely used Xilinx Vivado HLS high-level synthesis tool on a set of linear algebra benchmarks.