A fault-tolerant self-timed register

Self-timed technology, the foundations of which were laid by D. Muller, has been actively promoted in recent years not only on the "green" wave of energy saving technologies, but also in line with the increasing integration of digital chips to the nanoscale, where quantum effects begin to affect. The Institute of Informatics Problems - IPI RAN, continuing work of V.I. Warsawski's research group, has developed an extensive library of self-timed elements. In the UK, A. Yakovlev, who previously worked with V.I. Warsawski, is now engaged in this field. However, questions of fault tolerance self-timed circuits are still investigated insufficiently. We know that to create reliable, fault-tolerant and radiation-resistant electronic components, redundancy, or redundant structure, is needed. Redundant structures are necessary to design highly reliable, fault-tolerant, radiation-tolerant electronic components. Triplication is often used for this task: the three channels of a discrete circuit are connected with a special major gate which implements the choice function (e.g., 2-of-3, >2). This redundancy is commonly used in critical computing systems with passive fault-tolerance. As is known, such redundant structures provide reliability advantages not for the whole time range. In this case (to reserve self-timed circuits), the basic principle of self-timed, semi-modular, devices is violated. The authors propose another technique of using redundant transistor structures for fault-tolerant computing systems as an alternative to triple modular redundancy. The paper proposes and evaluates a combined backup of triggers of a self-timed register using transistor structures. We show the effectiveness of this redundancy, compared with triple modular redundancy.