Comparison of triple redundancy logic elements and quadrupled CMOS transistors

The article examines redundancy by quadrupling CMOS transistors by the example of a full adder. It is shown that in case there are more than two transistors in the original circuit transistor chain, it is necessary to perform the circuit decomposition due to the restrictions prohibiting the use of a serial connection of more than four transistors. Hardware costs and the probability of failure-free operation are evaluated in comparison with triple redundancy. The preference for quadrupling transistors is justified.