Technology and technique of the CMOS-chip learning experiment

The technique of the learning experiment of the chips with a CMOS structure is considered. The analysis of the constructive-technological features of the 765 series chips have carried out. The connection circuits and schemes of the main parameters measurement during the learning experiment are proposed. A choice of methods and means for the informative parameters control in the investigation tests is studied. The process of the sample size selecting is described. An approach to the development of the routine investigation tests is defined.