A Low Cost High Speed FPGA-Based Image Processing Framework

A Low Cost High Speed FPGA-Based Image Processing Framework

Автор: Mohammad Reza Mahmoodi, Sayed Masoud Sayedi

Журнал: International Journal of Modern Education and Computer Science (IJMECS) @ijmecs

Статья в выпуске: 3 vol.8, 2016 года.

Бесплатный доступ

In this paper, a high-speed and low-cost image processing framework based on MATLAB-FPGA interface is proposed that can be used in researches aiming at developing wide variety of not only image processing tasks but also many signal processing applications. In addition, this new framework could be exploited for several other tasks such as on-chip verification, using PC as an enormous external RAM for FPGA while preserving high speed data access, developing hardware-software co-designs, etc. The communication between FPGA and MATLAB is via 1Gbs Ethernet based on UDP/IP protocol which is very promising for high speed data transmission in point-to-point communications. UDP stack is efficiently designed in FPGA based on a fully pipelined architecture with minimum level of logic in order to reach high performance.. Dynamic data transmission between the UDP stack, memory and an arbitrary image processing module makes it possible to practically simulate, debug and implement most relevant applications. The hardware system is relatively low-cost and it consumes a negligible area of a Spartan-6 LXT45 Xilinx FPGA. Operating at 1 Gb/s, theoretically, the system is capable of processing 132 frames of 640*480 color images in a second. The effectiveness of the system is evaluated by means of both place and route simulation and practical implementation of a skin detection algorithm and a motion detector.

Еще

FPGA, MATLAB, Hardware Implementation, UDP Stack, Digital Signal Processing, Image Processing

Короткий адрес: https://sciup.org/15014844

IDR: 15014844

Список литературы A Low Cost High Speed FPGA-Based Image Processing Framework

  • U. Meyer-Baese, "Digital signal processing with field programmable gate arrays," Vol. 65. Heidelberg: Springer, 2007.
  • R. Woods, J. McAllister, Y. Yi, and G. Lightbody, "FPGA-based Implementation of Signal Processing Systems", John Wiley & Sons, 2008.
  • J. Cooley, and T. Tukey, "An algorithm for the machine calculation of complex Fourier series," Mathematics of computation 19, no. 90 (1965): 297-301.
  • C. D. Cunţan, I. Baciu, and M. Osaci. "Studies on the Necessity to Integrate the FPGA (Field Programmable Gate Array) Circuits in the Digital Electronics Lab Didactic Activity." International Journal of Modern Education & Computer Science 7.6 (2015).
  • T. Daghooghi, "Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA." International Journal of Modern Education and Computer Science (IJMECS) 5.5 (2013): 49.
  • B. Rashidi, and M. Sabahi, "High Performance FPGA Based Digital Space Vector PWM Three Phase Voltage Source Inverter," International Journal of Modern Education and Computer Science (IJMECS) 5.1 (2013): 62.
  • S. Kim, J. Park, S. Park, B. Koo, K. Shin, K. Suh, I. Kim, N. Eum, and K. Kim, "Hardware-software implementation of MPEG-4 video codec," ETRI journal 25, no. 6 (2003): 489-502.
  • S. Ramachandran, "Digital VLSI systems design," springer, 2007.
  • I. Kuon, and J. Rose, "Measuring the gap between FPGAs and ASICs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 26, no. 2 (2007): 203-215.
  • H. Parvez, and H. Mehrez, "Application-specific Mesh-based Heterogeneous FPGA Architectures," Springer, 2010.
  • R. Francis, J. Rose, and Z. G. Vranesic, "Field-programmable gate arrays," Vol. 180. Springer, 1992.
  • S. Haruyama, "FPGA in the Software Radio," IEEE communications Magazine (1999): 109.
  • National Instruments, "Reconfigurable Grid? FPGAs Versus DSPs for Power Electronics," 2011.
  • J. Rodriguez-Andina María, J. Moure, and M. Dolores Valdes, "Features, design tools, and application domains of FPGAs," Industrial Electronics, IEEE Transactions on 54, no. 4, pp.1810-1823, 2007.
  • R. Tessier, and W. Burleson, "Reconfigurable computing for digital signal processing: A survey." Journal of VLSI signal processing systems for signal, image and video technology 28, no. 1-2, pp. 7-27, 2001.
  • A. Banerjee, A. Sundar Dhar, and S. Banerjee, "FPGA realization of a CORDIC based FFT processor for biomedical signal processing," Microprocessors and Microsystems 25, no. 3, pp. 131-142, 2001.
  • M. R. Mahmoodi, H. Nikaein, Z. Fahimi, "A Parallel Architecture for High Speed BLAST Using FPGA," In Electrical Engineering (ICEE), 2014 International Conference on, IEEE, 2014. In press.
  • Fahimi, Z.; Dehghani, R., "IM3 injection technique for improving the linearity of an RF power amplifier," in Electrical Engineering (ICEE), 2015 23rd Iranian Conference on, vol., no., pp.1112-1117, 10-14 May 2015 doi: 10.1109/IranianCEE.2015.7146379L.
  • Guan, and A. Zhu, "Low-cost FPGA implementation of Volterra series-based digital predistorter for RF power amplifiers," IEEE Transactions on Microwave Theory and Techniques 58, no. 4, 2010.
  • X. Tan, S. Chen, Z. Zhou, and F. Zhang, "Face recognition from a single image per person: A survey," Pattern Recognition 39, no. 9 (2006): 1725-1745.
  • S. Kasap, K. Benkrid, and Y. Liu, "Design and Implementation of an FPGA-based Core for Gapped BLAST Sequence Alignment with the Two-Hit Method," Engineering Letters 16, no. 3 (2008): 443-452.
  • N. Alachiotis, S. Berger, A. Stamatakis, "A versatile UDP/IP based PC ↔ FPGA communication platform," Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on , vol., no., pp.1,6, 5-7 Dec. 2012.
  • A. Lofgren, L. Lodesten, S. Sjoholm, and H. Hansson, "An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity," In NORCHIP Conference, 2005. 23rd, pp. 94-97. IEEE, 2005.
  • M. R. Mahmoodi, S. M. Sayedi, and B. Mahmoodi, "Reconfigurable hardware implementation of gigabit UDP/IP stack based on spartan-6 FPGA," Information Technology and Electrical Engineering (ICITEE), 2014 6th International Conference on. IEEE, 2014.
  • K. Ross, and J. Kurose, "Computer Networking: A Top-Down Approach Featuring the Internet: Preliminary Edition," Addison-Wesley Longman Publishing Co., Inc., 1999.
  • M. R. Mahmoodi, S. M. Sayedi, "Boosting performance of face detection using an efficient skin detection algorithm," In Information Technology and Electrical Engineering (ICITEE), 2014 International Conference on, IEEE, 2014.
  • M. R. Mahmoodi, S. M. Sayedi, "A Face detection method based on kernel probability map", Computers and Electrical Engineering, Elsevier, 2015.
  • M. R. Mahmoodi, S. M. Sayedi, and F. Karimi, "Propagation from conservatively selected skin pixels using a multi-step multi-feature method," Electrical Engineering (ICEE), 2015 23rd Iranian Conference on. IEEE, 2015.
  • M. R. Mahmoodi, S. M. Sayedi, "A face detector based on color and texture." In Information Technology and Electrical Engineering (ICITEE), 2014 6th International Conference on 2014 Oct 7 (pp. 1-6). IEEE.
  • M. R. Mahmoodi, and S. M. Sayedi, "Leveraging Spatial Analysis on Homogeneous regions of Color Images for Skin Classification," Computer and Knowledge Engineering (ICCKE), 7th International Conference on, pp.1-6, IEEE, 29-30 Oct, 2014.
  • F. Herrmann, et al, "A gigabit udp/ip network stack in fpga," Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on. IEEE, 2009.
  • A. Dollas, et al. "An Open TCP/IP Core for Reconfigurable Logic," FCCM. Vol. 5. 2005.
  • W. Kühn, et al. "FPGA based compute nodes for high level triggering in PANDA," Journal of Physics: Conference Series. Vol. 119. No. 2. IOP Publishing, 2008.
  • P. Bomel, G. Gogniat, and J. Diguet, "A networked, lightweight and partially reconfigurable platform," Reconfigurable Computing: Architectures, Tools and Applications. Springer Berlin Heidelberg, 2008. 318-323.
  • Xilinx, "XAPP433: Embedded System Example: Web Server Design Using MicroBlaze Soft Processor," 2006.
  • N. Alachiotis, S. A. Berger, and A. Stamatakis, "Efficient PC-FPGA Communication over Gigabit Ethernet," Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on. IEEE, 2010.
Еще
Статья научная
QR-код для установки приложения SciUp Наведите камеру и скачайте бесплатное приложение SciUp