A model for estimating firmware execution time taking into account peripheral behavior
Автор: Dmytro V. Fedasyuk, Tetyana A. Marusenkova, Ratybor S. Chopey
Журнал: International Journal of Intelligent Systems and Applications @ijisa
Статья в выпуске: 6 vol.10, 2018 года.
Бесплатный доступ
The paper deals with the problem of estimating the execution time of firmware. Any firmware is bound to wait for a response from peripheral devices such as external memory chips, displays, analog-to-digital converters, etc. The firmware’s execution is frozen until the expected response is obtained. Thus, any firmware’s execution time depends not only on the computational resources of the embedded system being inspected but also on peripheral devices each of which is able to perform a set of operations during some random time period residing, however, within a known interval. The paper introduces a model of a computer application for evaluation of microcontroller-based embedded systems’ firmware’s execution time that takes into consideration the type of the microcontroller, the total duration of all the assembler-like instructions for a specific microcontroller, all the occasions of waiting for a response from hardware components, and the possible time periods for all the responses being waited for. Besides, we proposed the architecture of the computer application that assumes a reusable database retaining data on microcontrollers’ instructions.
Firmware execution time, execution time uncertainty, modeling, Monte-Carlo, embedded systems
Короткий адрес: https://sciup.org/15016495
IDR: 15016495 | DOI: 10.5815/ijisa.2018.06.03
Список литературы A model for estimating firmware execution time taking into account peripheral behavior
- S. Vasudevan, S. R, S. V and M. N, "Design and Development of an Embedded System for Monitoring the Health Status of a Patient", International Journal of Intelligent Systems and Applications, vol. 5, no. 4, pp. 64-71, 2013. doi:10.5815/ijisa.2013.04.06.
- O. Oyetoke, "A Practical Application of ARM Cortex-M3 Processor Core in Embedded System Engineering", International Journal of Intelligent Systems and Applications, vol. 9, no. 7, pp. 70-88, 2017. doi:10.5815/ijisa.2017.07.08.
- L. Insup, J. Leung and S. Son, Handbook of Real-Time and Embedded Systems. Boca Raton, Fla.: Chapman & Hall, 2008.
- R. Wilhelm, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, et al. "The worst-case execution-time problem — overview of methods and survey of tools", ACM Transactions on Embedded Computing Systems, vol. 7, no. 3, pp. 1-53, 2008. doi:10.1145/1347375.1347389
- P. Lokuciejewski and P. Marwedel, Worst-case execution time aware compilation techniques for real-time systems. New York: Springer, 2011.
- C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling et al. "Reliable and Precise WCET Determination for a Real-Life Processor", Embedded Software, pp. 469-485, 2001. doi:10.1007/3-540-45449-7_32.
- D. Stewart, "Measuring Execution Time and Real-Time Performance", in Embedded Systems Conference ESC-341/361, Boston, 2006.
- M. Wahler, E. Ferranti, R. Steiger, R. Jain and K. Nagy, "CAST: Automating Software Tests for Embedded Systems", 2012 IEEE Fifth International Conference on Software Testing, Verification and Validation, 2012. doi:10.1109/ICST.2012.126
- R. Kirner, "The WCET Analysis Tool CalcWcet167", Leveraging Applications of Formal Methods, Verification and Validation. Applications and Case Studies, pp. 158-172, 2012. doi:10.1007/978-3-642-34032-1_17.
- H. Aljifri, A. Pons and M. Tapia, "Tighten the computation of worst-case execution-time by detecting feasible paths", Conference Proceedings of the 2000 IEEE International Performance, Computing, and Communications Conference, 2000. doi:10.1109/PCCC.2000.830347.
- C. Healy, M. Sjödin, V. Rustagi, D. Whalley and R. Engelen, "Supporting timing analysis by automatic bounding of loop iterations", Real-Time Systems, vol. 18, no. 23, pp. 129-156, 2000. doi:10.1023/A:1008189014032.
- C. Healy and D. Whaley, "Tighter timing predictions by automatic detection and exploitation of value-dependent constraints", Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium, pp. 79-92, 1999. doi:10.1109/RTTAS.1999.777663.
- Y. Liu and G. Gomez, "Automatic accurate time-bound analysis for high-level languages", Lecture Notes in Computer Science, pp. 31-40, 1998. doi:10.1007/BFb0057778.
- J. Engblom, "Processor Pipelines and Static Worst-Case Execution Time Analy- sis", Dissertation for the Degree of Doctor of Philosophy in Computer Systems, Uppsala, 2002.
- L. Xianfeng, A. Roychoudhury and T. Mitra, "Modeling Out-of-Order Processors for Software Timing Analysis", 25th IEEE International Real-Time Systems Symposium, 2004. doi:10.1109/REAL.2004.33.
- S. Lim, Y. Bae, G. Jang, B. Rhee, S. Min, C. Park, et al. "An accurate worst case timing analysis for RISC processors", IEEE Transactions on Software Engineering, vol. 21, no. 7, pp. 593-604, 1995. doi:10.1109/32.392980.
- C. Healy, R. Arnold, F. Mueller, D. Whalley and M. Harmon, "Bounding pipeline and instruction cache performance", IEEE Transactions on Computers, vol. 48, no. 1, pp. 53-70, 1999. doi:10.1109/12.743411.
- F. Stappert and P. Altenbernd, "Complete worst-case execution time analysis of straight-line hard real-time programs", Journal of Systems Architecture, vol. 46, no. 4, pp. 339-355, 2000. doi:10.1016/S1383-7621(99)00010-7.
- C. Ferdinand, R. Heckmann, and H. Theiling. "Convenient user annotations for a WCET tool", International Workshop on Worst-Case Execution Time Analysis, pp 17–20, 2003.
- J. Engblom, A. Ermedahl and F. Stappert, "Structured Testing of Worst-Case Execution Time Analysis Methods", in Work-In-Progress Sessions of The 21st IEEE Real-Time Systems Symposium (RTSSWIP00), Orlando, Florida, 2000.
- D. Fedasyuk, R. Chopey and B. Knysh, "Architecture of a tool for automated testing the worst-case execution time of real-time embedded systems' firmware", 14th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics (CADSM), Lviv, Ukraine, 2017, pp. 278-282. doi:10.1109/cadsm.2017.7916134.
- R. Chopey, B. Knysh and D. Fedasyuk, "The model of software execution time remote testing", in 7th International youth science forum “LITTERIS ET ARTIBUS”, Lviv, Ukraine, 2017, pp. 398-402.
