Design of a Radiation Hardened Register File for Highly Reliable Microprocessors
Автор: Ramin Rajaei
Журнал: International Journal of Engineering and Manufacturing(IJEM) @ijem
Статья в выпуске: 5 vol.6, 2016 года.
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In this paper, a powerful bit upset masking (PBUM) technique for design of a high reliable register file is proposed. This technique is based on the triple modular redundancy (TMR) technique with the key capability of double faulty bit masking in every triad of bits while the TMR structure, only masks one fault in a triad. We implemented a 64-bit register file comprised of 64 registers protected with the proposed PBUM technique on FPGA. Our simulation results reveal that, over the TMR and some Hamming code-based techniques, our design offers a very higher robustness against radiation induced soft errors. Also, the proposed PBUM technique imposes a lower delay than its counterparts at the expense of a little higher area overhead. To reduce the area overhead, an area-efficient strategy is suggested that balances the reliability improvement and the area overhead. We show that, our technique using this area-aware strategy still has the highest reliability among the other considered techniques.
Triple Modular Redundancy (TMR), Single Event Upset (SEU), Multiple Bit Upset (MBU), Register File, Fault Tolerance
Короткий адрес: https://sciup.org/15014411
IDR: 15014411
Список литературы Design of a Radiation Hardened Register File for Highly Reliable Microprocessors
- A. Dutta, N. A. Touba, "Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code," In 25th IEEE VLSI Test Symmposium (VTS'07) (2007).
- A. J. Ricketts, M. Mutyam, N. Vijaykrishnan, N. J. Irwin, "Investigating Simple Low Latency Reliable Multiported Register Files," VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium, vol., no., pp.375-382, 9-11 March 2007.
- R. Rajaei, M. Tabandeh, B. Rashidian, "Single Event Upset immune latch circuit design using C-Element," in Proc. of the IEEE 9th International Conference on ASIC, China, pp. 280-283, 2011.
- S. Esmaeeli, M. Hosseini, B. V. Vahdat, B. Rashidian, "A multi-bit error tolerant register file for a high reliable embedded processor," 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2011.
- R. Rajaei, B. Asgari, M. Tabandeh, M. Fazeli, "Design of Robust SRAM Cells Against Single Event Multiple Effects for Nanometer Technologies," IEEE Transactions on Device and Materials Reliability, 2015.
- B. Alidoosti, M. H. Moaiyeri, "An Energy-Efficient and Robust Voltage Level Converter for Nanoelectronics," International Journal of Modern Education and Computer Science (IJMECS), 7(5), 2015.
- R. Rajaei, B. Asgari, M. Tabandeh, M. Fazeli, "Single Event Multiple Upset-Tolerant SRAM Cell Designs for Nano-scale CMOS Technology," Turkish Journal of Electrical Engineering & Computer Sciences, 2016.
- M. Kaviani, H. Sharifi, M. Dolatshahi, K. Navi, "Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor," International Journal of Engineering and Manufacturing (IJEM), 2016.
- R. Naseer, R. Z. Bhatti, J. Draper, "Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology," Circuits and Systems, MWSCAS '06. 49th IEEE International Midwest Symposium on , vol.1, no., pp.515-519, 6-9 Aug. 2006.
- V. Chandra, R. Aitken, "Impact of voltage scaling on nanoscale SRAM reliability," Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
- R. Rajaei, M. Tabandeh, M. Fazeli, "Low Cost Soft Error Hardened Latch Designs for Nano-scale CMOS Technology in presence of Process Variation," Microelectronic Reliability, Elsevier, 2013.
- R. Gong, W. Chen, F. Liu, K. Dai, Z. Wang, "Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique," in 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), Arlington, Virginia, USA. Pages 184-196, IEEE Computer Society, 2006.
- G. Memik, M.T. Kandemir, and O. Ozturk "Increasing Register File Immunity to Transient Errors", Proceedings of Design, Automation and Test in Europe (DATE'05), Munich, Germany, vol. 1, pp. 586-591, Mar. 2005.
- R. Hentschke, F. Marques, F. Lima, L. Carro, A. Susin, R. Reis, "Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy". Proceedings of the 15 th Symposium on Integrated Circuits and Systems Design (SBCCI'02).
- R. W. Hamming, "Error Correcting and Error Detecting Codes", Bell Sys. Tech. Journal, Vol. 29, pp. 147-160, Apr. 1950.
- S. M. Reddy, "A Class of Linear Codes for Error Control in Byte-per-Package Organized Memory Systems", IEEE Trans. On Computers, Vol. C-27, pp. 455-458, May. 1978.
- C. L. Chen, "Error Correcting Codes with Byte Error Detection Capability", IEEE Trans. On Computers, Vol. C-32, pp. 615-621, May 1983.
- M. Fazeli, S. A. Ahmadian, S.G. Miremadi, "A Low Energy Soft Error-Tolerant Architecture for Register File in Embedded Processors, 11th IEEE High Assurance Systems Engineering Symposium, (HASE 2008), Nanjing, China, 2008.
- M. Ebrahimi, A. Evans, M.B. Tahoori, E. Costenaro, D. Alexandrescu, V. Chandra, R. Seyyedi, "Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015.
- L. Chen, M. Ebrahimi, M.B. Tahoori, "Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths," Journal of Electronic Testing: Theory and Applications (JETTA), Springer, 2015.
- R. Rajaei, S. Bakhtavari, F. Eslaminasab, Radiation Hardening by Design for Nonvolatile Magnetic Flip-Flops, The 1st International Conference on New Research Achievements in Electrical and Computer Engineering, Tehran, Iran, 2016.
- B. Alidoosti, M. H. Moaiyeri, "An Energy-Efficient and Robust Voltage Level Converter for Nanoelectronics," International Journal of Modern Education and Computer Science (IJMECS), 7(5), 2015.
- R. Rajaei, "Radiation Hardened Design of Nonvolatile MRAM-based FPGA," IEEE Transactions on Magnetics, 2016.
- M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, "MiBench: A free, commercially representative embedded benchmark suite," in Proc. IEEE 4th Annu. Workshop Workload Characterization, Austin, TX, Dec. 2001, pp. 3–14.
