Design of Low Power Sequential Circuit by using Adiabatic Techniques

Design of Low Power Sequential Circuit by using Adiabatic Techniques

Автор: Priyanka Ojha, Charu Rana

Журнал: International Journal of Intelligent Systems and Applications(IJISA) @ijisa

Статья в выпуске: 8 vol.7, 2015 года.

Бесплатный доступ

Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit.

Adiabatic Switching, Energy Dissipation, AC Power Supply, Inverter, D Latch And D Flip-Flop

Короткий адрес: https://sciup.org/15010741

IDR: 15010741

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