Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor
Автор: Maede Kaviani, Hojjat Sharifi, Mahdi Dolatshahi, Keivan Navi
Журнал: International Journal of Engineering and Manufacturing(IJEM) @ijem
Статья в выпуске: 1 vol.6, 2016 года.
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BICMOS circuits are interesting for designers when a high speed output driver is required especially in I/O circuits. Buffer is an important block in high speed circuits, so designing a buffer with high drive capability has a great effect on circuits with large load capacitor. This paper presents a new BiCMOS buffer which uses 32nm technology node for CMOS transistors and 0.18um technology node for BJT transistors. The proposed buffer operates properly in voltage ranges from 0.8v to 1.5v. The capacitor range is from 0.5pf to 200pf; the overshoot of the output in this capacitor range is less than 10% of the supply voltage that is negligible. The proposed design has improvements in delay for about %88 respectively compared to similar CMOS buffers with high capacitor values.
Buffer, BiCMOS, High load, Capacitor, Low power, Inverter
Короткий адрес: https://sciup.org/15014391
IDR: 15014391
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